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ADAU1462WBCPZ300 PDF预览

ADAU1462WBCPZ300

更新时间： 2024-02-24 19:02:02
品牌 Logo 应用领域
亚德诺 - ADI 商用集成电路
页数 文件大小 规格书
202页 9593K
描述
SigmaDSP Compact Digital Audio Processor

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ADAU1462WBCPZ300 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN,
针数：72Reach Compliance Code：compliant
风险等级：5.6Samacsys Description：SigmaDSP Digital Audio Processor
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：S-XQCC-N72
长度：10 mm湿度敏感等级：3
功能数量：1端子数量：72
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260座面最大高度：1 mm
最大供电电压 (Vsup)：1.26 V最小供电电压 (Vsup)：1.14 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：10 mm

ADAU1462WBCPZ300 数据手册

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Data Sheet  
ADAU1462/ADAU1466  
APPLICATIONS INFORMATION  
Component Placement  
PCB DESIGN CONSIDERATIONS  
Place all 100 nF bypass capacitors, which are recommended for  
every analog, digital, and PLL power ground pair, as near as  
possible to theADAU1462/ADAU1466. Bypass each of the  
AVDD, DVDD, PVDD, and IOVDD supply signals on the board  
with an additional single bulk capacitor (10 μF to 47 μF).  
A solid ground plane is necessary for maintaining signal  
integrity and minimizing EMI radiation. If the PCB has two  
ground planes, they can be stitched together using vias that are  
spread evenly throughout the board.  
Power Supply Bypass Capacitors  
Keep all traces in the crystal resonator circuit (see Figure 14) as  
short as possible to minimize stray capacitance. Do not connect  
any long board traces to the crystal oscillator circuit components  
because such traces may affect crystal startup and operation.  
Bypass each power supply pin to its nearest appropriate ground  
pin with a single 100 nF capacitor and, optionally, with an  
additional 10 nF capacitor in parallel. Make the connections to  
each side of the capacitor as short as possible, and keep the trace  
on a single layer with no vias. For maximum effectiveness, place  
the capacitor either equidistant from the power and ground pins  
or, when equidistant placement is not possible, slightly nearer to  
the power pin (see Figure 84). Establish the thermal connections  
to the planes on the far side of the capacitor.  
Grounding  
Use a single ground plane in the application layout. Place all  
components in an analog signal path away from digital signals.  
Exposed Pad PCB Design  
The device package includes an exposed pad for improved heat  
dissipation. When designing a board for such a package,  
consider the following:  
POWER GROUND  
Place a copper layer, equal in size to the exposed pad, on all  
layers of the board, from top to bottom. Connect the copper  
layers to a dedicated copper board layer (see Figure 87).  
CAPACITOR  
TO POWER  
TO GROUND  
Figure 84. Recommended Power Supply Bypass Capacitor Layout  
Figure 87. Exposed Pad Layout Example—Side View  
Typically, a single 100 nF capacitor for each power ground pin  
pair is sufficient. However, if there is excessive high frequency  
noise in the system, use an additional 10 nF capacitor in parallel  
(see Figure 85). Place the 10 nF capacitor between the devices  
and the 100 nF capacitor, and establish the thermal connections  
on the far side of the 100 nF capacitor.  
Place vias such that all layers of copper are connected,  
allowing for efficient heat and energy conductivity. For an  
example, see Figure 88, which shows 49 vias arranged in  
a 7 × 7 grid in the pad area.  
VIA TO  
POWER PLANE  
VIA TO  
GROUND PLANE  
100nF  
10nF  
Figure 88. Exposed Pad Layout Example—Top View  
For detailed information, see the AN-772 Application Note,  
A Design and Manufacturing Guide for the Lead Frame Chip  
Scale Package (LFCSP).  
Figure 85. Layout for Multiple Power Supply Bypass Capacitors  
To provide a current reservoir in case of sudden current spikes,  
use a 10 μF capacitor for each named supply (DVDD, AVDD,  
PVDD, and IOVDD) as shown in Figure 86.  
BULK BYPASS CAPACITORS  
PLL Filter  
To minimize jitter, connect the single resistor and two capacitors  
in the PLL filter to the PLLFILT and PVDD pins with short  
traces.  
3.3V  
AVDD PVDD IOVDD DVDD  
+
+
+
+
10µF  
10µF  
10µF  
10µF  
Figure 86. Bulk Bypass Capacitor Schematic  
Rev. B | Page 197 of 202  
 
 
 
 
 
 
 
 
 
 
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