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ADA4939-2YCPZ-R2 PDF预览

ADA4939-2YCPZ-R2

更新时间: 2024-01-13 19:16:06
品牌 Logo 应用领域
亚德诺 - ADI 驱动器
页数 文件大小 规格书
24页 518K
描述
Ultralow Distortion Differential ADC Driver

ADA4939-2YCPZ-R2 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN,针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.4
差分输出:YES驱动器位数:1
输入特性:DIFFERENTIAL接口集成电路类型:LINE DRIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-XQCC-N24
JESD-609代码:e3长度:4 mm
湿度敏感等级:3功能数量:2
端子数量:24最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified最大接收延迟:
座面最大高度:1 mm最大供电电压:5.25 V
最小供电电压:3 V标称供电电压:5 V
表面贴装:YES技术:BIPOLAR
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4 mmBase Number Matches:1

ADA4939-2YCPZ-R2 数据手册

 浏览型号ADA4939-2YCPZ-R2的Datasheet PDF文件第18页浏览型号ADA4939-2YCPZ-R2的Datasheet PDF文件第19页浏览型号ADA4939-2YCPZ-R2的Datasheet PDF文件第20页浏览型号ADA4939-2YCPZ-R2的Datasheet PDF文件第21页浏览型号ADA4939-2YCPZ-R2的Datasheet PDF文件第23页浏览型号ADA4939-2YCPZ-R2的Datasheet PDF文件第24页 
ADA4939-1/ADA4939-2  
LAYOUT, GROUNDING, AND BYPASSING  
As a high speed device, the ADA4939 is sensitive to the  
PCB environment in which it operates. Realizing its superior  
performance requires attention to the details of high speed  
PCB design. This section shows a detailed example of how the  
ADA4939-1 was addressed.  
The power supply pins should be bypassed as close to the device  
as possible and directly to a nearby ground plane. High frequency  
ceramic chip capacitors should be used. It is recommended that  
two parallel bypass capacitors (1000 pF and 0.1 μF) be used for  
each supply. The 1000 pF capacitor should be placed closer to  
the device. Further away, low frequency bypassing should be  
provided, using 10 μF tantalum capacitors from each supply  
to ground.  
The first requirement is a solid ground plane that covers as  
much of the board area around the ADA4939-1 as possible.  
However, the area near the feedback resistors (RF), gain resistors  
(RG), and the input summing nodes (Pin 2 and Pin 3) should be  
cleared of all ground and power planes (see Figure 51). Clearing  
the ground and power planes minimizes any stray capacitance at  
these nodes and prevents peaking of the response of the amplifier  
at high frequencies.  
Signal routing should be short and direct to avoid parasitic  
effects. Wherever complementary signals exist, a symmetrical  
layout should be provided to maximize balanced performance.  
When routing differential signals over a long distance, PCB  
traces should be close together, and any differential wiring  
should be twisted such that loop area is minimized. Doing this  
reduces radiated energy and makes the circuit less susceptible  
to interference.  
The thermal resistance, θJA, is specified for the device, including  
the exposed pad, soldered to a high thermal conductivity four-layer  
circuit board, as described in EIA/JESD 51-7.  
1.30  
0.80  
1.30 0.80  
Figure 51. Ground and Power Plane Voiding in Vicinity of RF and RG  
Figure 52. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)  
1.30  
TOP METAL  
GROUND PLANE  
0.30  
PLATED  
VIA HOLE  
POWER PLANE  
BOTTOM METAL  
Figure 53. Cross-Section of Four-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)  
Rev. 0 | Page 22 of 24  
 
 

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