AD9985A
Pin Type
Mnemonic
VD
VDD
PVD
GND
Function
Value
3.3 V
3.3 V
3.3 V
0 V
Pin No.
Power Supply
Analog Power Supply
Output Power Supply
PLL Power Supply
Ground
26, 27, 39, ꢀ2, ꢀ5, ꢀ6, 51, 52, 59, 62
11, 22, 23, 69, 78, 79
3ꢀ, 35
1, 10, 20, 21, 2ꢀ, 25, 28, 32, 36, ꢀ0, ꢀ1,
ꢀꢀ, ꢀ7, 50, 53, 60, 61, 63, 68, 80
Serial Port (2-Wire) SDA
Serial Port Data I/O
Serial Port Data Clock (100 kHz maximum)
Serial Port Address Input 1
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
57
56
55
SCL
A0
Table 5. Pin Function Descriptions
Pin
Inputs
RIN
Description
Analog Input for Red Channel.
Analog Input for Green Channel.
GIN
BIN
Analog Input for Blue Channel. High impedance inputs that accept the red, green, and blue channel graphics
signals, respectively. (The three channels are identical, and can be used for any colors, but colors are assigned for
convenient reference.) They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be
ac-coupled to these pins to support clamp operation.
HSYNC
Horizontal Sync Input. This input receives a logic signal that establishes the horizontal timing reference and
provides the frequency reference for pixel clock generation. The logic sense of this pin is controlled by serial
Register 0x0E, Bit 6 (Hsync polarity). Only the leading edge of Hsync is active; the trailing edge is ignored. When
Hsync polarity = 0, the falling edge of Hsync is used. When Hsync polarity = 1, the rising edge is active. The input
includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V.
VSYNC
SOGIN
Vertical Sync Input. This is the input for vertical sync.
Sync-on-Green Input. This input is provided to assist with processing signals with embedded sync, typically on the
green channel. The pin is connected to a high speed comparator with an internally generated threshold. The
threshold level can be programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the
negative peak of the input signal. The default voltage threshold is 150 mV. When connected to an ac-coupled
graphics signal with embedded sync, it produces a noninverting digital output on SOGOUT. (This is usually a
composite sync signal, containing both vertical and horizontal sync information that must be separated before
passing the horizontal sync signal to Hsync.) When not used, this input should be left unconnected. For more
details on this function and how it should be configured, refer to the Sync-on-Green section.
CLAMP
COAST
External Clamp Input. This logic input can be used to define the time during which the input signal is clamped to
ground. It should be exercised when the reference dc level is known to be present on the analog input channels,
typically during the back porch of the graphics signal. The CLAMP pin is enabled by setting control bit clamp
function to 1, (Register 0x0F, Bit 7, default is 0). When disabled, this pin is ignored and the clamp timing is
determined internally by counting a delay and duration from the trailing edge of the Hsync input. The logic sense
of this pin is controlled by clamp polarity Register 0x0F, Bit 6. When not used, this pin must be grounded and
clamp function programmed to 0.
Clock Generator Coast Input (Optional). This input can be used to cause the pixel clock generator to stop
synchronizing with Hsync and continue producing a clock at its current frequency and phase. This is useful when
processing signals from sources that fail to produce horizontal sync pulses during the vertical interval. The Coast
signal is generally not required for PC-generated signals. The logic sense of this pin is controlled by Coast polarity
(Register 0x0F, Bit 3). When not used, this pin can be grounded and Coast polarity programmed to 1, or tied high
(to VD through a 10 kΩ resistor) and Coast polarity programmed to 0. Coast polarity defaults to 1 at power-up.
Outputs
HSOUT
Horizontal Sync Output. A reconstructed and phase-aligned version of the Hsync input. Both the polarity and
duration of this output can be programmed via serial bus registers. By maintaining alignment with DATACK and
Data outputs, data timing with respect to horizontal sync can always be determined.
VSOUT
Vertical Sync Output. A reconstructed and phase-aligned version of the video Vsync. The polarity of this output
can be controlled via a serial bus bit. The placement and duration in all modes is set by the graphics transmitter.
SOGOUT
Sync-on-Green Slicer Output. This pin outputs either the signal from the sync-on-green slicer comparator or an
unprocessed but delayed version of the Hsync input. See the sync processing block diagram (Figure 1ꢀ) to view
how this pin is connected. (Apart from slicing off SOG, the output from this pin gets no other additional process-
ing on the AD9985A. Vsync separation is performed via the sync separator.)
Rev. 0 | Page 9 of 32
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