AD9963BCPZRL

更新时间： 2024-01-13 14:02:58

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
60页	974K
描述
10-/12-Bit, Low Power, Broadband MxFE

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AD9963BCPZRL 数据手册

AD9961/AD9963

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AUX33V

AUXADCREF

RXQP

54 DLLFILT

53 DLL18V

52 DVDD18

51 DRVDD

50 NC

PIN 1

INDICATOR

RXQN

RXGND

RXBIAS

RX18V

RX33V

RX18VF

RXCML 10

RXGND 11

RXIN 12

RXIP 13

LDO_EN

49 NC

48 TXD0

47 TXD1

46 TXD2

45 TXD3

44 TXD4

43 TXD5

42 TXD6

41 TXD7

40 TXD8

39 TXD9

38 TXIQ/TXnRX

37 TXCLK

AD9961

(TOP VIEW)

RESET 15

SCLK 16

CS 17

SDIO 18

NOTES

1. EXPOSED PAD MUST BE SOLDERED TO PCB.

2. NC = NO CONNECT.

Figure 2. AD9961 Pin Configuration

Table 8. AD9961 Pin Function Descriptions

Pin No.

Mnemonic

Description

AUX33V

Analog Supply for the Auxiliary ADC and Auxiliary DACs (3.3 V 5%, 1.8 V 5% If Auxiliary ADC Is

Powered Down).

AUXADCREF

RXQP, RXQN

RXGND

Reference Output (Or Input) for Auxiliary ADC.

Differential ADC Q Inputs. The default full-scale input voltage range is 1.56 V p-p differential.

Receive Path Ground.

External Bias Resistor Connection. An optional 10 kΩ resistor can be connected between this pin and the

analog ground to improve the accuracy of the full-scale range of the Rx ADCs.

3, 4

5, 11

RXBIAS

RX18V

RX33V

Output of RX18V Voltage Regulator.

Input to RX18V and RX18VF Voltage Regulators (2.5 V to 3.3 V). If LDOs are not being used, short Pin 8 to

Pin 7.

RX18VF

RXCML

Output of RX18VF Voltage Regulator.

ADC Common-Mode Voltage Output.

12, 13

RXIN, RXIP

LDO_EN

Differential ADC I Inputs. The default full-scale input voltage range is 1.56 V p-p differential.

Control Pin for LDOs (GND = Disable all LDOs, Float = Enable DVDD18 LDO Only, DRVDD = Enable All

LDOs).

RESET

SCLK

Reset. Active low to reset the configuration registers to default values and reset device.

Clock Input for Serial Port.

Active Low Chip Select.

19, 34

SDIO

DGND

Bidirectional Data Line for Serial Port.

Digital Core Ground.

20, 33, 51 DRVDD

Input/Output Pad Ring Supply Voltage (1.8 V to 3.3 V).

ADC Output Data in Full Duplex Mode. ADC output data and DAC input data in half-duplex mode.

Not Connected.

21 to 30

TRXD9 to TRXD0

31, 32,

49, 50

TRXIQ

Output Signal Indicating from Which ADC the Output Data Is Sourced.

Rev. 0 | Page 9 of 60

1...6 7 8910 11 12...60

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