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AD9963BCPZ PDF预览

AD9963BCPZ

更新时间: 2024-01-06 09:09:15
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
60页 974K
描述
10-/12-Bit, Low Power, Broadband MxFE

AD9963BCPZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:VQCCN,针数:72
Reach Compliance Code:unknown风险等级:5.58
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:S-XQCC-N72
长度:10 mm湿度敏感等级:NOT APPLICABLE
功能数量:1端子数量:72
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:VQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, VERY THIN PROFILE
峰值回流温度(摄氏度):260座面最大高度:1 mm
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:NOT SPECIFIED
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:10 mmBase Number Matches:1

AD9963BCPZ 数据手册

 浏览型号AD9963BCPZ的Datasheet PDF文件第52页浏览型号AD9963BCPZ的Datasheet PDF文件第53页浏览型号AD9963BCPZ的Datasheet PDF文件第54页浏览型号AD9963BCPZ的Datasheet PDF文件第56页浏览型号AD9963BCPZ的Datasheet PDF文件第57页浏览型号AD9963BCPZ的Datasheet PDF文件第58页 
AD9961/AD9963  
POWER SUPPLY CONFIGURATION EXAMPLES  
POWER SUPPLIES  
There are numerous ways of configuring the power supplies  
powering the AD9961/AD9963. Two power supply  
configuration examples are shown in Figure 94 and Figure 95.  
The AD9961/AD9963 power distributions are shown in Figure 93.  
The functional blocks labeled Rx ANLG, Rx ADCs, SPI and  
digital core, clocking, and DLL operate from 1.8 V supplies. The  
functional blocks labeled Tx DACs, AUX DACs and digital I/O  
operate over a supply voltage range from 1.8 V to 3.3 V. The  
auxiliary ADC operates from a 3.3 V supply.  
Figure 94 shows a 3.3 V only power supply configuration. In  
this case, all of the internal circuits that require 1.8 V supplies  
are powered from the on-chip regulators. The LDO_EN pin is  
set high, and all of the internal LDOs are enabled. The transmit  
DAC, auxiliary converters, and I/O pads run from a 3.3 V supply.  
TXVDD(2)  
DLL18V  
AUX33V  
AUX ADCs  
AUX DACs  
Tx DACs  
REG 0x61 = 0x00  
AD9961/AD9963  
DLL  
LDO  
LDO  
RX18V  
RX33V  
Rx ANLG  
Rx ADCs  
CLOCKING  
LDO  
LDO  
CLK18V  
SPI AND  
DIGITAL  
CORE  
DVDD18V  
RX18VF  
LDO  
DRVDD(3)  
DIGITAL I/O  
3.3V  
AD9961/AD9963  
Figure 94. 3.3 V Only Supply Configuration  
Figure 93. AD9961/AD9963 Power Distribution Block Diagram  
Figure 95 shows a power supply configuration where all 1.8 V  
voltage rails are powered by external supplies. The LDO_EN  
pin is left floating, and all of the internal LDOs except  
DVDD18V are disabled. The transmit DAC, auxiliary  
converters and I/O pads run from a 3.3 V supply.  
The 1.8 V only blocks can be supplied directly with 1.8 V by  
using the RX18V, RX18VF, DLL18V, CLK18V, and DVDD18V  
supply pins. In this mode, the on-chip voltage regulators must  
be disabled. To provide optimal ESD protection for the device,  
the inputs of the LDO regulators should not be left floating.  
When unused, the LDO regulator inputs should be tied to one  
of the LDO outputs (for example, if RX33V is unused, tie  
RX33V to either RX18V or RX18VF).  
AD9961/AD9963  
When the LDO regulators are used, the RX18V, RX18VF,  
DLL18V, CLK18V, and DVDD18V pins should be decoupled to  
ground with a 0.1 µF or larger capacitor. The LDO inputs can  
operate over a range from 2.5 V to 3.3 V.  
The LDO_EN pin (Pin 14) is a three-state input pin that  
controls the operation of the LDOs. When LDO_EN is high, all  
of the LDOs are enabled. When LDO_EN is low, all of the  
LDOs are disabled. When LDO_EN is floating or approximately  
DRVDD/2, only the DVDD18V LDO is enabled. All of the  
LDOs except the DVDD18V LDO can be independently  
disabled through serial port control as well by writing to  
Register 0x61.  
1.8V  
3.3V  
Figure 95. 3.3 V and 1.8 V Supply Configuration  
POWER DISSIPATION  
The AD9961/AD9963 power dissipation is highly dependent on  
operating conditions. Table 30 and Figure 96 to Figure 103 show  
the typical current consumption by power supply domain under  
different operating conditions.  
The three DRVDD pins are internally connected together,  
therefore, these pins must be connected to the same voltage.  
The voltage applied to these pins affects the timing of the device  
as noted in the Digital Interfaces section.  
The current draw from the 1.8 V supplies are independent of  
whether they are supplied by the on-chip regulators or by an  
external 1.8 V supply. The quiescent current of the LDO regulators  
are about 100 µA.  
The TXVDD and AUX33V supplies can operate over a range  
from 1.8 V to 3.3 V. It should be noted that the auxiliary ADC  
requires AUX33V to be 3.3 V for operation. The performance  
of the Tx DACs vary with the TXVDD supply as indicated in  
the Table 1 and Figure 4 to Figure 11.  
The current drawn from the AUX33V supply by the auxiliary ADC  
is typically 350 µA. The 10-bit auxiliary DACs each typically draw  
275 µA from the AUX33V supply. The 12-bit auxiliary DACs  
typically draw 550 µA each from the AUX33V supply.  
Rev. 0 | Page 55 of 60  
 
 
 
 
 

AD9963BCPZ 替代型号

型号 品牌 替代类型 描述 数据表
AD9963BCPZRL ADI

完全替代

10-/12-Bit, Low Power, Broadband MxFE

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