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AD9951YSV-REEL7 PDF预览

AD9951YSV-REEL7

更新时间: 2024-02-06 10:10:21
品牌 Logo 应用领域
亚德诺 - ADI DSP外围设备微控制器和处理器外围集成电路时钟
页数 文件大小 规格书
28页 789K
描述
400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

AD9951YSV-REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:HTFQFP,针数:48
Reach Compliance Code:unknown风险等级:5.72
边界扫描:NO最大时钟频率:400 MHz
JESD-30 代码:S-PQFP-G48JESD-609代码:e0
长度:7 mm低功率模式:YES
湿度敏感等级:NOT SPECIFIED端子数量:48
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):220认证状态:COMMERCIAL
座面最大高度:1.2 mm最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR
Base Number Matches:1

AD9951YSV-REEL7 数据手册

 浏览型号AD9951YSV-REEL7的Datasheet PDF文件第19页浏览型号AD9951YSV-REEL7的Datasheet PDF文件第20页浏览型号AD9951YSV-REEL7的Datasheet PDF文件第21页浏览型号AD9951YSV-REEL7的Datasheet PDF文件第23页浏览型号AD9951YSV-REEL7的Datasheet PDF文件第24页浏览型号AD9951YSV-REEL7的Datasheet PDF文件第25页 
AD9951  
INSTRUCTION BYTE  
The instruction byte contains the following information:  
Table 7.  
MSB  
D6  
D5  
D4  
D3  
D2  
D1  
LSB  
R/Wb  
X
X
A4  
A3  
A2  
A1  
A0  
serial port is in LSB first format. The instruction byte must be  
written in the format indicated by Control Register 0x00 <8>. If  
the AD9951 is in LSB first mode, the instruction byte must be  
written from least significant bit to most significant bit.  
R/Wb—Bit 7 of the instruction byte determines whether a read  
or write data transfer will occur after the instruction byte write.  
Logic High indicates read operation. Logic 0 indicates a write  
operation.  
For MSB first operation, the serial port controller will generate  
the most significant byte (of the specified register) address first  
followed by the next lesser significant byte addresses until the  
I/O operation is complete. All data written to (read from) the  
AD9951 must be (will be) in MSB first order. If the LSB mode is  
active, the serial port controller will generate the least signifi-  
cant byte address first followed by the next greater significant byte  
addresses until the I/O operation is complete. All data written to  
(read from) the AD9951 must be (will be) in LSB first order.  
X, X—Bits 6 and 5 of the instruction byte are Don’t Care.  
A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte  
determine which register is accessed during the data transfer  
portion of the communications cycle.  
SERIAL INTERFACE PORT PIN DESCRIPTION  
SCLK—Serial Clock. The serial clock pin is used to synchronize  
data to and from the AD9951 and to run the internal state  
machines. SCLK maximum frequency is 25 MHz.  
Example Operation  
CSB—Chip Select Bar. CSB is active low input that allows more  
than one device on the same serial communications line. The  
SDO and SDIO pins will go to a high impedance state when this  
input is high. If driven high during any communications cycle,  
To write the amplitude scale factor register in MSB first format,  
apply an instruction byte of 0x02 (serial address is 00010(b)).  
From this instruction, the internal controller will generate an  
internal byte address of 0x07 (see the register map) for the first  
data byte written and an internal address of 0x08 for the next  
byte written. Since the amplitude scale factor register is two  
bytes wide, this ends the communication cycle.  
that cycle is suspended until  
is reactivated low. Chip select  
CS  
can be tied low in systems that maintain control of SCLK.  
SDIO — Serial Data I/O. Data is always written into the  
AD9951 on this pin. However, this pin can be used as a  
bidirectional data line. Bit 7 of Register Address 0x00 controls  
the configuration of this pin. The default is Logic 0, which  
configures the SDIO pin as bidirectional.  
To write the amplitude scale factor register in LSB first format,  
apply an instruction byte of 0x40. From this instruction, the  
internal controller will generate an internal byte address of  
0x08 (see the register map) for the first data byte written and an  
internal address of 0x07for the next byte written. Since the  
amplitude scale factor register is two bytes wide, this ends the  
communication cycle.  
SDO—Serial Data Out. Data is read from this pin for protocols  
that use separate lines for transmitting and receiving data. In the  
case where the AD9951 operates in a single bidirectional I/O  
mode, this pin does not output data and is set to a high imped-  
ance state.  
Power-Down Functions of the AD9951  
The AD9951 supports an externally controlled or hardware  
power-down feature as well as the more common software pro-  
grammable power-down bits found in previous ADI DDS products.  
IOSYNC—It synchronizes the I/O port state machines without  
affecting the addressable registers contents. An active high in-  
put on the IOSYNC pin causes the current communication  
cycle to abort. After IOSYNC returns low (Logic 0), another  
communication cycle may begin, starting with the instruction  
byte write.  
The software control power-down allows the DAC, PLL, input  
clock circuitry, and digital logic to be individually powered  
down via unique control bits (CFR1<7:4>). With the exception  
of CFR1<6>, these bits are not active when the externally con-  
trolled power-down pin (PWRDWNCTL) is high. External  
power-down control is supported on the AD9951 via the  
PWRDWNCTL input pin. When the PWRDWNCTL input pin  
is high, the AD9951 will enter a power-down mode based on  
the CFR1<3> bit. When the PWRDWNCTL input pin is low,  
the external power-down control is inactive.  
MSB/LSB TRANSFERS  
The AD9951 serial port can support both most significant bit  
(MSB) first or least significant bit (LSB) first data formats. This  
functionality is controlled by the Control Register 0x00 <8> bit.  
The default value of Control Register 0x00 <8> is low (MSB  
first). When Control Register 0x00 <8> is set high, the AD9951  
Rev. 0 | Page 22 of 28  
 

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