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AD9951

更新时间: 2024-01-21 21:02:49
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 789K
描述
400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

AD9951 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:HTFQFP,针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.6
边界扫描:NO最大时钟频率:400 MHz
JESD-30 代码:S-PQFP-G48JESD-609代码:e3
长度:7 mm低功率模式:YES
湿度敏感等级:3端子数量:48
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:7 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR
Base Number Matches:1

AD9951 数据手册

 浏览型号AD9951的Datasheet PDF文件第20页浏览型号AD9951的Datasheet PDF文件第21页浏览型号AD9951的Datasheet PDF文件第22页浏览型号AD9951的Datasheet PDF文件第24页浏览型号AD9951的Datasheet PDF文件第25页浏览型号AD9951的Datasheet PDF文件第26页 
AD9951  
When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is  
high, the AD9951 is put into a fast recovery power-down mode.  
In this mode, the digital logic and the DAC digital logic are  
powered down. The DAC bias circuitry, PLL, oscillator, and  
clock input circuitry is NOT powered down.  
Table 8 indicates the logic level for each power-down bit that  
drives out of the AD9951 core logic to the analog section and  
the digital clock generation section of the chip for the external  
power-down operation.  
Layout Considerations  
For the best performance, the following layout guidelines  
should be observed. Always provide the analog power supply  
(AVDD) and the digital power supply (DVDD) on separate  
supplies, even if just from two different voltage regulators  
driven by a common supply. Likewise, the ground connections  
(AGND, DGND) should be kept separate as far back to the  
source as possible (i.e., separate the ground planes on a local-  
ized board, even if the grounds connect to a common point in  
the system). Bypass capacitors should be placed as close to the  
device pin as possible. Usually, a multitiered bypassing scheme  
consisting of a small high frequency capacitor (100 pF) placed  
close to the supply pin and progressively larger capacitors (0.1 µF,  
10 µF) further away from the actual supply source works best.  
When the CFR1<3> bit is high, and the PWRDWNCTL input  
pin is high, the AD9951 is put into the full power-down mode.  
In this mode, all functions are powered down. This includes the  
DAC and PLL, which take a significant amount of time to  
power up.  
When the PWRDWNCTL input pin is high, the individual  
power-down bits (CFR1<7>, <5:4>) are invalid (Don’t Care)  
and unused. When the PWRDWNCTL input pin is low, the  
individual power-down bits control the power-down modes of  
operation.  
Note that the power-down signals are all designed such that a  
Logic 1 indicates the low power mode and a Logic 0 indicates  
the active or powered up mode.  
Table 8. Power-Down Control Functions  
Control  
Mode Active  
Description  
PWRDWNCTL = 0 CFR1<3> Don’t Care  
Software Control  
Digital Power-Down = CFR1<7>  
DAC Power-Down = CFR1<5>  
Input Clock Power-Down = CFR1<4>  
Digital Power-Down = 1’b1  
PWRDWNCTL = 1 CFR1<3> = 0  
PWRDWNCTL = 1 CFR1<3> = 1  
External Control,  
Fast Recovery Power-Down Mode  
DAC Power-Down = 1’b0  
Input Clock Power-Down = 1’b0  
Digital Power-Down = 1’b1  
DAC Power-Down = 1’b1  
External Control,  
Full Power-Down Mode  
Input Clock Power-Down = 1’b1  
Rev. 0 | Page 23 of 28  
 

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