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AD9944KCPRL

更新时间： 2024-01-02 08:42:17

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	672K
描述
Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors

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数据手册

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AD9944KCPRL 数据手册

AD9943/AD9944

CCD MODE TIMING

CCD

SIGNAL

N + 1

N + 2

N + 9

N + 10

t_ID

SHP

t_S1

t_S2

t_CP

SHD

DATACLK

t_OD

N – 10

OUTPUT

DATA

N – 9

N – 8

N – 1

NOTES

1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.

2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.

Figure 14. CCD Mode Timing

HORIZONTAL

BLANKING

EFFECTIVE PIXELS

OPTICAL BLACK PIXELS

DUMMY PIXELS

EFFECTIVE PIXELS

CCD

SIGNAL

CLPOB

PBLK

OUTPUT

DATA

OB PIXEL DATA

DUMMY BLACK

EFFECTIVE DATA

EFFECTIVE PIXEL DATA

NOTES

1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.

2. PBLK SIGNAL IS OPTIONAL.

3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.

Figure 15. Typical CCD Mode Line Clamp Timing

Rev. B | Page 17 of 20

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