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AD9944KCPRL

更新时间： 2024-01-28 07:29:03

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	672K
描述
Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors

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AD9944KCPRL 数据手册

AD9943/AD9944

CIRCUIT DESCRIPTION AND OPERATION

DC RESTORE

INTERNAL

REF

6dB TO 40dB

VGA

2V FULL SCALE

0.1µF

CCDIN

10/12

10-/12-BIT

ADC

DOUT

CDS

CLPOB

OPTICAL BLACK

CLAMP

8-BIT

DAC

DIGITAL

FILTERING

VGA GAIN

CLAMP LEVEL

Figure 12. CCD Mode Block Diagram

The AD9943/AD9944 signal processing chain is shown in

OPTICAL BLACK CLAMP

Figure 12. Each processing step is essential for achieving a high

quality image from the raw CCD pixel data.

The optical black clamp loop is used to remove residual offsets

in the signal chain and to track low frequency variations in the

CCD’s black level. During the optical black (shielded) pixel

interval on each line, the ADC output is compared with the

fixed black level reference selected by the user in the clamp level

the correction value is applied to the ADC input through a D/A

converter. Normally, the optical black clamp loop is turned on

once per horizontal line, but this loop can be updated more

slowly to suit a particular application. If external digital

clamping is used during the post processing, the optical black

clamping for the AD9943/AD9944 may be disabled using

Bit D3 in the operation register. Refer to Table 9 and Figure 10

and Figure 11.

DC RESTORE

To reduce the large dc offset of the CCD output signal, a dc

restore circuit is used with an external 0.1 µF series coupling

capacitor. This restores the dc level of the CCD signal to

approximately 1.5 V, which is compatible with the 3 V single

supply of the AD9943/AD9944.

CORRELATED DOUBLE SAMPLER

The CDS circuit samples each CCD pixel twice to extract video

information and reject low frequency noise. The timing shown

in Figure 14 illustrates how the two CDS clocks, SHP and SHD,

are used, respectively, to sample the reference level and data

level of the CCD signal. The CCD signal is sampled on the

rising edges of SHP and SHD. Placement of these two clock

signals is critical for achieving the best performance from the

CCD. An internal SHP/SHD delay (t_ID) of 3 ns is caused by

internal propagation delays.

When the loop is disabled, the clamp level register may still be

used to provide programmable offset adjustment. Horizontal

timing is shown in Figure 15. The CLPOB pulse should be

placed during the CCD’s optical black pixels. It is recommended

that the CLPOB pulse be used during valid CCD dark pixels.

The CLPOB pulse should be a minimum of 20 pixels wide to

minimize clamp noise. Shorter pulse widths may be used, but

clamp noise may increase and the loop’s ability to track low

frequency variations in the black level is reduced.

Rev. B | Page 15 of 20

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