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AD9937KCP PDF预览

AD9937KCP

更新时间: 2024-01-20 23:46:46
品牌 Logo 应用领域
亚德诺 - ADI 消费电路商用集成电路
页数 文件大小 规格书
44页 399K
描述
CCD Signal Processor with Precision Timing⑩ Generator

AD9937KCP 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFN包装说明:MO-220-VLLD-2, LFCSP-56
针数:56Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.71Is Samacsys:N
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-XQCC-N56
JESD-609代码:e0长度:8 mm
功能数量:1端子数量:56
最高工作温度:85 °C最低工作温度:-25 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V表面贴装:YES
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8 mmBase Number Matches:1

AD9937KCP 数据手册

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AD9937  
VDD  
(INPUT)  
1
1
tPWR  
INTERNAL  
POWER-ON  
AUTO-RESET  
(LO-ACTIVE)  
2
VCKM  
4
5
6
7
SERIAL  
WRITES  
OUTCONT  
(REGISTER  
CONTROLLED)  
1V  
VD  
(OUTPUT)  
ODD FIELD  
EVEN FIELD  
ODD FIELD  
1H  
HD  
(OUTPUT)  
V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B,  
OFD, H1(A, B, C, D)  
DIGITAL  
OUTPUTS  
RS, H2(A, B), LM  
2
3
tSETTINGS  
tDELAY  
VCLK  
NOTES  
1
THE INTERNAL POWER-ON AUTO RESET TIME tPWR = 1.0ms REGARDLESS OF THE VCLK CLOCK FREQUENCY.  
2
IT TAKES 500s FOR VCLK TO SETTLE ONCE THE DIG_STBY REGISTER HAS BEEN PROGRAMMED.  
3
IT TAKES FOUR VCKM CLOCK CYCLES FROM WHEN OUTCONT IS ASSERTED HIGH UNTIL THE VD, HD, AND DIGITAL OUTPUT DATA IS VALID.  
Figure 37. Recommended Power-Up Sequence  
Table XVIII. Start-Up Polarities  
(While OUTCONT = LO)  
POWER-UP FOR MASTER MODE  
When the AD9937 is powered up, the following sequence is  
recommended. (Refer to Figure 37 for each step.)  
Output  
OUTCONT = LO  
1. Turn on power supplies for AD9937.  
V1A/B  
V2  
V3A/B  
V4  
TG1A  
TG1B  
TG3A  
TG3B  
OFD  
H1(AD)  
H2(A, B)  
LM  
HI  
HI  
HI  
HI  
HI  
HI  
HI  
HI  
HI  
HI  
LO  
LO  
LO  
2. The internal power-on auto-reset circuit will deassert  
1.0 ms after VDD settles. (All internal registers are reset to  
the default values.)  
3. The VCKM clock can be applied as soon as VDD settles.  
4. Reset the internal AD9937 registers: write a 0x000000 to  
the SW_RESET register (addr 0x00). This will set all inter-  
nal register values to their default values. (This step is optional  
because the internal power-on reset circuit is applied at  
power-up.)  
5. Write a 1 to the DIG_STBY and AFE_STBY registers  
(addr 0x02). This will put the digital and analog circuits into  
the normal operating mode.  
6. Program all control, system, and mode registers.  
7. Write a 1 to the OUTCONT_REG (addr 0x01). This will put  
the digital outputs into the normal operating mode. The inter-  
nal OUTCONT will be asserted high on the rising edge of the  
32nd SCK clock when writing to the OUTCONT_REG.  
RS  
REV. 0  
–39–  

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