Datasheet > AD9889B/PCB

AD9889B/PCB

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
12页	301K
描述
High Performance HDMI/DVI Transmitter

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AD9889B/PCB 数据手册

AD9889B

Preliminary Technical Data

Pin No.

LFCSP

Mnemonic Type¹Description

BGA

LQFP

1, 48, 49

1, 61, 62,

63, 64

D5, D6, D7, E7

DVDD

1.8 V Power Supply for Digital and I/O Power Supply. These

pins supply power to the digital logic and I/Os. They should

be filtered and as quiet as possible.

15, 16, 17,

16, 19, 20, 21

G4, G5, J1

PVDD

1.8 V PLL Power Supply. The most sensitive portion of the

AD9889B is the clock generation circuitry. These pins provide

power to the clock PLL. The designer should provide quiet,

noise-free power to these pins.

64, paddle

on bottom

side

15, 17, 18, 22,

26, 32, 39, 42,

43, 59, 60, 79,

D4, E4, F4, J4, G6,

J6, K6, F7, G7, H9,

GND

Ground. The ground return for all circuitry on-chip. It is

recommended that the AD9889B be assembled on a single,

solid ground plane with careful attention given to ground

current paths.

SDA

SCL

C³

Serial Port Data I/O. This pin serves as the serial port data I/O

slave for register access. Supports CMOS logic levels from

1.8 V to 3.3 V.

Serial Port Data Clock. This pin serves as the serial port data

clock slave for register access. Supports CMOS logic levels

from 1.8 V to 3.3 V.

F10

E10

MDA

C³

Serial Port Data I/O Master to HDCP Key EEPROM. Supports

CMOS logic levels from 1.8 V to 3.3 V.

Serial Port Data Clock Master to HDCP Key EEPROM. Supports

CMOS logic levels from 1.8 V to 3.3 V.

Serial Port Data I/O to Receiver. This pin serves as the master

to the DDC bus. 5 V CMOS logic level.

Serial Port Data Clock to Receiver. This pin serves as the

master clock for the DDC bus. 5 V CMOS logic level.

MCL

DDCSDA

DDCSCL

G10

¹I = input, O = output, P = power supply, C = control.

²Pin J7 (BGA), Pin 26 (LFCSP), and Pin 33 (LQFP) are dual function pins: I²C selection and power-down control. The I²C selection function occurs at power-up; the power-

down control function occurs whenever the state of the pin is changed from its original state at power-up.

³For a full description of the 2-wire serial interface and its functionality obtain documentation by contacting NDA from flatpanel_apps@analog.com.

Rev. PrA | Page 8 of 12

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