AD9879
PCB DESIGN CONSIDERATIONS
The DVDD portion of the plane brings the current used to power
the digital portion of the MxFE to the device. This should be
treated similar to the 3VDD power plane and be kept from
going underneath the MxFE or analog components. The MxFE
should largely sit above the AVDD portion of the power plane.
Although the AD9879 is a mixed-signal device, the part should
be treated as an analog component. The digital circuitry on-chip
has been specially designed to minimize the impact that the
digital switching noise will have on the operation of the analog
circuits. Following the power, grounding, and layout recommen-
dations in this section will help the user get the best performance
from the MxFE.
The AVDD and DVDD power planes may be fed from the same
low noise voltage source; however, they should be decoupled
from each other to prevent the noise generated in the DVDD
portion of the MxFE from corrupting the AVDD supply. This
can be done by using ferrite beads between the voltage source
and DVDD and between the source and AVDD. Both DVDD
and AVDD should have a low ESR, bulk decoupling capacitor on
the MxFE side of the ferrite as well as a low ESR, ESL decoupling
capacitors on each supply pin (i.e., the AD9879 requires 17
power supply decoupling caps). The decoupling caps should be
placed as close to the MxFE supply pins as possible. An example
of the proper decoupling is shown in the AD9875 evaluation
board schematic.
Component Placement
If the three following guidelines of component placement are
followed, chances for getting the best performance from the
MxFE are greatly increased. First, manage the path of return
currents flowing in the ground plane so that high frequency
switching currents from the digital circuits do not flow on the
ground plane under the MxFE or analog circuits. Second, keep
noisy digital signal paths and sensitive receive signal paths as
short as possible. Third, keep digital (noise generating) and analog
(noise susceptible) circuits as far away from each other as possible.
In order to best manage the return currents, pure digital circuits
that generate high switching currents should be closest to the
power supply entry. This will keep the highest frequency return
current paths short, and prevent them from traveling over the
sensitive MxFE and analog portions of the ground plane. Also,
these circuits should be generously bypassed at each device
which will further reduce the high frequency ground currents.
The MxFE should be placed adjacent to the digital circuits,
such that the ground return currents from the digital sections
will not flow in the ground plane under the MxFE. The analog
circuits should be placed furthest from the power supply.
Ground Planes
In general, if the component placing guidelines discussed earlier
can be implemented, it is best to have at least one continuous
ground plane for the entire board. All ground connections should
be made as short as possible. This will result in the lowest imped-
ance return paths and the quietest ground connections.
If the components cannot be placed in a manner that would keep
the high frequency ground currents from traversing under the
MxFE and analog components, it may be necessary to put current
steering channels into the ground plane to route the high fre-
quency currents around these sensitive areas. These current
steering channels should be made only when and where necessary.
The AD9879 has several pins which are used to decouple sensi-
tive internal nodes. These pins are REFIO, REFB10, REFT10,
REFB12, and REFT12. The decoupling capacitors connected
to these points should have low ESR and ESL. These capacitors
should be placed as close to the MxFE as possible and be con-
nected directly to the analog ground plane.
Signal Routing
The digital Rx and Tx signal paths should be kept as short as
possible. Also, the impedance of these traces should have a
controlled impedance of about 50 Ω. This will prevent poor
signal integrity and the high currents that can occur during
undershoot or overshoot caused by ringing. If the signal traces
cannot be kept shorter than about 1.5 inches, then series termi-
nation resistors (33 Ω to 47 Ω) should be placed close to all
signal sources. It is a good idea to series terminate all clock
signals at their source regardless of trace length.
The resistor connected to the FSADJ pin and the RC network
connected to the PLLFILT pin should also be placed close to
the device and connected directly to the analog ground plane.
Power Planes and Decoupling
The AD9879 evaluation board demonstrates a good power
supply distribution and decoupling strategy. The board has four
layers; two signal layers, one ground plane and one power plane.
The power plane is split into a 3 VDD section which is used for
the 3 V digital logic circuits, a DVDD section that is used to
supply the digital supply pins of the AD9879, an AVDD section
that is used to supply the analog supply pins of the AD9879,
and a VANLG section that supplies the higher voltage analog
components on the board. The 3 VDD section will typically have
the highest frequency currents on the power plane and should be
kept the furthest from the MxFE and analog sections of the board.
The receive (I in, Q in, and RF in) signals are the most sensitive
signals on the entire board. Careful routing of these signals is
essential for good receive path performance. The Rx+/– signals
form a differential pair and should be routed together as a pair.
By keeping the traces adjacent to each other, noise coupled onto
the signals will appear as common mode and will be largely
rejected by the MxFE receive input. Keeping the driving point
impedance of the receive signal low and placing any low-pass
filtering of the signals close to the MxFE will further reduce the
possibility of noise corrupting these signals.
–22–
REV. 0
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