AD9875
D EFINITIO NS O F SP ECIFICATIO NS
CLO CK JITTER
T he clock jitter is a measure of the intrinsic jitter of the PLL
generated clocks. It is a measure of the jitter from one rising
and of the clock with respect to another edge of the clock nine
cycles later.
O FFSET ERRO R
First transition should occur for an analog value 1/2 LSB above
negative full scale. Offset error is defined as the deviation of the
actual transition from that point.
GAIN ERRO R
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. T he last transition should occur for an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.
D IFFERENTIAL NO NLINEARITY ERRO R
(D NL, NO MISSING CO D ES)
An ideal converter exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicates that all 1024
codes respectively, must be present over all operating ranges.
INP UT REFERRED NO ISE
INTEGRAL NO NLINEARITY ERRO R (INL)
T he RMS output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in LSB,
and converted to an equivalent voltage. T his results in a noise
figure that can be directly referred to the Rx input of the AD9875.
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs 1/2 LSB
before the first code transition. “positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. T he deviation
is measured from the middle of each particular code to the true
straight line.
SIGNAL-TO -NO ISE AND D ISTO RTIO N RATIO (SINAD )
SINAD is the ratio of the RMS value of the measured input
signal to the RMS sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
T he value for SINAD is expressed in decibels.
P H ASE NO ISE
Single-sideband phase noise power density is specified relative
to the carrier (dBc/Hz) at a given frequency offset (1 kHz) from
the carrier. Phase noise can be measured directly on a generated
single tone with a spectrum analyzer that supports noise marker
measurements. It detects the relative power between the carrier
and the offset (1 kHz) sideband noise and takes the resolution
bandwidth (rbw) into account by subtracting 10 log(rbw). It
also adds a correction factor that compensates for the imple-
mentation of the resolution bandwidth, log display and detector
characteristic.
EFFECTIVE NUMBER O F BITS (ENO B)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76) dB/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
SIGNAL-TO -NO ISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. T he value for SNR is
expressed in decibels.
O UTP UT CO MP LIANCE RANGE
T he range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation, resulting in nonlinear per-
formance or breakdown.
TO TAL H ARMO NIC D ISTO RTIO N (TH D )
T HD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
SP URIO US–FREE D YNAMIC RANGE (SFD R)
T he difference, in dB, between the rms amplitude of the DACs
output signal (or ADC’s input signal) and the peak spurious
signal over the specified bandwidth (Nyquist bandwidth unless
otherwise noted).
P O WER SUP P LY REJECTIO N
Power Supply Rejection specifies the converters maximum
full-scale change when the supplies are varied from nominal to
minimum and maximum specified voltages.
P IP ELINE D ELAY (LATENCY)
T he number of clock cycles between conversion initiation and
the associated output data being made available.
REV. 0
–7–
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