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AD9857ASTZ1 PDF预览

AD9857ASTZ1

更新时间: 2022-06-05 18:07:58
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
40页 1072K
描述
CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter

AD9857ASTZ1 数据手册

 浏览型号AD9857ASTZ1的Datasheet PDF文件第31页浏览型号AD9857ASTZ1的Datasheet PDF文件第32页浏览型号AD9857ASTZ1的Datasheet PDF文件第33页浏览型号AD9857ASTZ1的Datasheet PDF文件第35页浏览型号AD9857ASTZ1的Datasheet PDF文件第36页浏览型号AD9857ASTZ1的Datasheet PDF文件第37页 
AD9857  
HARDWARE-CONTROLLED DIGITAL  
POWER-DOWN  
POWER MANAGEMENT CONSIDERATIONS  
The thermal impedance for the AD9857 80-lead LQFP package  
is θJA = 35°C/W. The maximum allowable power dissipation  
using this value is calculated using ΔT = P × θJA.  
The hardware-controlled method for reducing power is to apply  
a Logic 1 to the DPD pin. Restarting the part after a digital  
power-down is accomplished by applying a Logic 0 to the DPD  
pin. The DPD pin going to Logic 0 can occur simultaneously  
with the activation of TxENABLE.  
ΔT  
P =  
θJA  
150 85  
The user notices some time delay between invoking the digital  
power-down function and the actual reduction in power. This is  
due to an automatic routine that clears the signal processing  
chain before stopping the clocks. Clearing the signal processing  
chain before powering down ensures that the AD9857 is ready  
to transmit when digital power-down mode is deactivated (see  
the Clearing the CIC filter section for details).  
P =  
35  
P =1.85W  
The AD9857 power dissipation is at or below this value when  
the SYSCLK frequency is at 200 MHz or lower with all optional  
features enabled. The maximum power dissipation occurs while  
operating the AD9857 as a quadrature modulator at the  
maximum system clock frequency with TxENABLE in a logic  
high state 100ꢀ of the time the device is powered. Under these  
conditions, the device operates with all possible circuits enabled  
at maximum speed.  
SOFTWARE-CONTROLLED DIGITAL POWER-  
DOWN  
The software-controlled method for reducing digital power  
between transmissions is simply an enable or disable of an  
automatic power-down function. When enabled, digital power-  
down between bursts occurs automatically after all data has  
passed the AD9857 signal processing path.  
Significant power saving may be seen by using a TxENABLE  
signal that toggles low during times when the device does not  
modulate.  
When the AD9857 senses the TxENABLE input indicates the  
end of a transmission, an on-chip timer is used to verify that the  
data has completed transmission before stopping the internal  
clocks that drive the signal processing chain memory elements.  
As with the hardware activation method, clock synchronization  
is maintained and the PDCLK output continues to run. An  
active high signal on TxENABLE automatically restarts the  
internal clocks, allowing the next burst transmission to start  
immediately.  
The thermal impedance of the AD9857 package was measured  
in a controlled temperature environment at temperatures  
ranging from 28°C to 85°C with no air flow. The device under  
test was soldered to an AD9857 evaluation board and operated  
under conditions that generate maximum power dissipation.  
The thermal resistance of a package can be thought of as a  
thermal resistor that exists between the semiconductor surface  
and the ambient air. The thermal impedance of a package is  
determined by package material and its physical dimensions.  
The dissipation of the heat from the package is directly  
dependent upon the ambient air conditions and the physical  
connection made between the IC package and the PCB.  
Adequate dissipation of power from the AD9857 relies upon all  
power and ground pins of the device being soldered directly to  
copper planes on a PCB.  
The automatic digital power-down between bursts is enabled by  
writing the Control Register 01h<2> bit high. Writing the  
Control Register 01h<2> bit low disables the function.  
FULL SLEEP MODE  
When coming out of full sleep mode, it is necessary to wait for  
the PLL lock indicator to go high. Full Sleep mode functionality  
is provided by programming one of the Control Registers  
(01h<3>). When the Full-Sleep bit is set to a Logic 1, the device  
shuts down both its digital and analog sections. During full  
sleep mode, the contents of the registers of the AD9857 are  
maintained. This mode yields the minimum possible device  
power dissipation.  
Many variables contribute to the operating junction  
temperature within a device. They include:  
1. Package style  
2. Selection mode of operation  
3. Internal system clock speed  
4. Supply voltage  
5. Ambient temperature  
The power dissipation of the AD9857 in a given application is  
determined by several operating conditions. Some of these  
conditions, such as supply voltage and clock speed, have a direct  
relationship with power dissipation. The most important factors  
affecting power dissipation follow.  
Rev. C | Page 34 of 40  
 

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