AD9835

更新时间： 2024-01-20 04:14:21

品牌	Logo	应用领域
亚德诺 - ADI		数据分配系统
页数	文件大小	规格书
16页	163K
描述
50 MHz CMOS Complete DDS

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技术参数
数据手册

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AD9835 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.08
Is Samacsys：	N	边界扫描：	NO
最大时钟频率：	50 MHz	外部数据总线宽度：	1
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	5 mm	低功率模式：	YES
湿度敏感等级：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出数据总线宽度：	1	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.1 mm
子类别：	DSP Peripherals	最大供电电压：	5.25 V
最小供电电压：	4.25 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR
Base Number Matches：	1

AD9835 数据手册

AD9835

Table I. Control Registers

Size Description

Table V. Commands

C3 C2 C1 C0 Command

FREQ0 REG

32 Bits Frequency Register 0. This de-

fines the output frequency, when

FSELECT = 0, as a fraction of the

MCLK frequency.

32 Bits Frequency Register 1. This de-

fines the output frequency, when

FSELECT = 1, as a fraction of the

MCLK frequency.

Write 16 Phase bits (Present 8 Bits + 8 Bits

in Defer Register) to Selected PHASE

REG.

Write 8 Phase bits to Defer Register.

FREQ1 REG

Write 16 Frequency bits (Present 8 Bits

+ 8 Bits in Defer Register) to Selected

FREQ REG.

Write 8 Frequency bits to Defer Register.

PHASE0 REG 12 Bits Phase Offset Register 0. When

PSEL0 = PSEL1 = 0, the contents

Bits D9 (PSEL0) and D10 (PSEL1) are

used to Select the PHASE REG when

SELSRC = 1. When SELSRC = 0, the

PHASE REG is selected using the pins

PSEL0 and PSEL1 Respectively.

Bit D11 is used to select the FREQ REG

when SELSRC = 1. When SELSRC = 0,

the FREQ REG is selected using the pin

FSELECT.

This command is used to control the

PSEL0, PSEL1 and FSELECT bits

using only one write. Bits D9 and D10

are used to select the PHASE REG and

Bit 11 is used to select the FREQ REG

when SELSRC = 1. When SELSRC = 0,

the PHASE REG is selected using the

pins PSEL0 and PSEL1 and the FREQ

REG is selected using the pin FSELECT.

of this register are added to the

output of the phase accumulator.

PHASE1 REG 12 Bits Phase Offset Register 1. When

PSEL0 = 1 and PSEL1 = 0, the con-

tents of this register are added to the

output of the phase accumulator.

PHASE2 REG 12 Bits Phase Offset Register 2. When

PSEL0 = 0 and PSEL1 = 1, the

contents of this register are added to

the output of the phase accumulator.

PHASE3 REG 12 Bits Phase Offset Register 3. When

PSEL0 = PSEL1 = 1, the contents

of this register are added to the

output of the phase accumulator.

Table II. Addressing the Registers

Reserved. Configures the AD9835 for

Test Purposes.

Destination Register

FREG0 REG 8 L LSBs

FREG0 REG 8 H LSBs

FREG0 REG 8 L MSBs

FREG0 REG 8 H MSBs

FREG1 REG 8 L LSBs

FREG1 REG 8 H LSBs

FREG1 REG 8 L MSBs

FREG1 REG 8 H MSBs

PHASE0 REG 8 LSBs

PHASE0 REG 8 MSBs

PHASE1 REG 8 LSBs

PHASE1 REG 8 MSBs

PHASE2 REG 8 LSBs

PHASE2 REG 8 MSBs

PHASE3 REG 8 LSBs

PHASE3 REG 8 MSBs

Table VI. Controlling the AD9835

D15 D14 Command

1 0

Selects source of Control for the PHASE and

FREQ Registers and Enables Synchronization. Bit

D13 is the SYNC Bit. When this bit is High, read-

ing of the FSELECT, PSEL0 and PSEL1 bits/pins

and the loading of the Destination Register with

data is synchronized with the rising edge of MCLK.

The latency is increased by 2 MCLK cycles when

SYNC = 1. When SYNC = 0, the loading of the

data and the sampling of FSELECT/PSEL0/PSEL1

occurs asynchronously. Bit D12 is the Select

Source Bit (SELSRC). When this bit Equals 1, the

PHASE/FREQ REG is Selected using the bits

FSELECT, PSEL0 and PSEL1. When SELSRC =

0, the PHASE/FREQ REG is Selected using the

pins FSELECT, PSEL0 and PSEL1.

Table III. 32-Bit Frequency Word

Sleep, Reset and Clear. D13 is the SLEEP bit. When

this bit equals 1, the AD9835 is powered down, inter-

nal clocks are disabled and the DAC's current sources

and REFOUT are turned off. When SLEEP = 0, the

AD9835 is powered up. When RESET (D12) = 1,

the phase accumulator is set to zero phase which

corresponds to an analog output of full scale. When

CLR (D11) = 1, SYNC and SELSRC are set to

zero. CLR automatically resets to zero.

16 MSBs

8 H MSBs 8 L MSBs

16 LSBs

8 H LSBs 8 L LSBs

Table IV. 12-Bit Frequency Word

4 MSBs (The 4 MSBs of the

8-Bit Word Loaded = 0)

8 LSBs

–6–

REV. 0

1...3 4 567 8 9...16

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