AD9835

更新时间： 2024-01-13 18:23:52

品牌	Logo	应用领域
亚德诺 - ADI		数据分配系统
页数	文件大小	规格书
16页	163K
描述
50 MHz CMOS Complete DDS

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中文翻译

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技术参数
数据手册

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AD9835 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.08
Is Samacsys：	N	边界扫描：	NO
最大时钟频率：	50 MHz	外部数据总线宽度：	1
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	5 mm	低功率模式：	YES
湿度敏感等级：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出数据总线宽度：	1	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.1 mm
子类别：	DSP Peripherals	最大供电电压：	5.25 V
最小供电电压：	4.25 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATOR
Base Number Matches：	1

AD9835 数据手册

AD9835

PIN FUNCTION DESCRIPTIONS

Pin # Mnemonic

Function

ANALOG SIGNAL AND REFERENCE

FS ADJUST

Full-Scale Adjust Control. A resistor (R_SET) is connected between this pin and AGND. This determines

the magnitude of the full-scale DAC current. The relationship between R_SETand the full-scale current is

as follows:

IOUT_FULL-SCALE= 12.5 × V_REFIN/R_SET

_REFIN= 1.21 V nominal, R_SET= 3.9 kΩ typical

REFIN

Voltage Reference Input. The AD9835 can be used with either the onboard reference, which is available

from pin REFOUT, or an external reference. The reference to be used is connected to the REFIN pin.

The AD9835 accepts a reference of 1.21 V nominal.

Voltage Reference Output. The AD9835 has an onboard reference of value 1.21 V nominal. The refer-

ence is made available on the REFOUT pin. This reference is used as the reference to the DAC by con-

necting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.

REFOUT

IOUT

Current Output. This is a high impedance current source. A load resistor should be connected between

IOUT and AGND.

Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling

ceramic capacitor should be connected between COMP and AVDD.

COMP

POWER SUPPLY

DVDD

Positive Power Supply for the Digital Section. A 0.1 µF decoupling capacitor should be connected be-

tween DVDD and DGND. DVDD can have a value of +5 V ± 5%.

DGND

AGND

AVDD

Digital Ground.

Analog Ground.

Positive Power Supply for the Analog Section. A 0.1 µF decoupling capacitor should be connected be-

tween AVDD and AGND. AVDD can have a value of +5 V ± 5%.

DIGITAL INTERFACE AND CONTROL

MCLK

Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK.

The output frequency accuracy and phase noise are determined by this clock.

SCLK

Serial Clock, Logic Input. Data is clocked into the AD9835 on each falling SCLK edge.

Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.

Data Synchronization Signal, Logic Input. When this input is taken low, the internal logic is informed

that a new word is being loaded into the device.

SDATA

FSYNC

FSELECT

Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the

phase accumulator. The frequency register to be used can be selected using the pin FSELECT or the bit

FSELECT. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state

when an MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an

uncertainty of one MCLK cycle as to when control is transferred to the other frequency register. To avoid

any uncertainty, a change on FSELECT should not coincide with an MCLK rising edge. When the bit is

being used to select the frequency register, the pin FSELECT should be tied to DGND.

11, 12 PSEL0, PSEL1 Phase Select Input. The AD9835 has four phase registers. These registers can be used to alter the value

being input to the COS ROM. The contents of the phase register are added to the phase accumula-

tor output, the inputs PSEL0 and PSEL1 selecting the phase register to be used. Alternatively, the

phase register to be used can be selected using bits PSEL0 and PSEL1. Like the FSELECT input,

PSEL0 and PSEL1 are sampled on the rising MCLK edge. Therefore, these inputs need to be in

steady state when an MCLK rising edge occurs or there is an uncertainty of one MCLK cycle as to

when control is transferred to the selected phase register. When the phase registers are being con-

trolled by the bits PSEL0 and PSEL1, the pins should be tied to DGND.

REV. 0

–5–

1 2 3 456 7 8...16

中文翻译

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与AD9835相关器件

型号	品牌	获取价格	描述	数据表
AD9835BRU	ADI	获取价格	50 MHz CMOS Complete DDS
AD9835BRU-REEL	ADI	获取价格	50 MHz Direct Digital Synthesizer, Waveform Generator
AD9835BRU-REEL7	ADI	获取价格	50 MHz Direct Digital Synthesizer, Waveform Generator
AD9835BRUZ	ADI	获取价格	50 MHz Direct Digital Synthesizer, Waveform Generator
AD9835BRUZ-REEL	ADI	获取价格	50 MHz Direct Digital Synthesizer, Waveform Generator
AD9835BRUZ-REEL7	ADI	获取价格	50 MHz Direct Digital Synthesizer, Waveform Generator
AD9835EB	ADI	获取价格	Evaluation Board for the AD9835 Direct Digital Synthesizer
AD9837	ADI	获取价格	Low Power, 8.5 mW, 2.3 V to 5.5 V, Programmable Waveform Generator
AD9837ACPZ-RL	ADI	获取价格	Low Power, 8.5 mW, 2.3 V to 5.5 V, Programmable Waveform Generator
AD9837ACPZ-RL7	ADI	获取价格	Low Power, 8.5 mW, 2.3 V to 5.5 V, Programmable Waveform Generator

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