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AD9824KCPZRL PDF预览

AD9824KCPZRL

更新时间: 2024-02-28 12:54:02
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
25页 466K
描述
Complete 14-Bit 30 MSPS CCD Signal Processor

AD9824KCPZRL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Contact Manufacturer零件包装代码:QFN
包装说明:VQCCN,针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.02
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:S-XQCC-N48
JESD-609代码:e3长度:7 mm
湿度敏感等级:3功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-20 °C封装主体材料:UNSPECIFIED
封装代码:VQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:0.9 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
温度等级:OTHER端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:7 mmBase Number Matches:1

AD9824KCPZRL 数据手册

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AD9824  
chain at the specified gain setting. The output noise can be  
converted to an equivalent voltage using the relationship  
1 LSB = (ADC Full Scale/2N codes) where N is the bit resolution  
of the ADC. For the AD9824, 1 LSB is 125 µV.  
DEFINITIONS OF SPECIFICATIONS  
Differential Nonlinearity (DNL)  
An ideal ADC exhibits code transitions that are exactly 1 LSB  
apart. DNL is the deviation from this ideal value. Thus, every code  
must have a finite width. No missing codes guaranteed to 14-bit  
resolution indicates that all 16,384 codes, respectively, must  
be present over all operating conditions.  
Power Supply Rejection (PSR)  
The PSR is measured with a step change applied to the supply  
pins. This represents a high frequency disturbance on the  
AD9824’s power supply. The PSR specification is calculated  
from the change in the data outputs for a given step change in  
the supply voltage.  
Peak Nonlinearity  
Peak nonlinearity, a full signal chain specification, refers to the  
peak deviation of the output of the AD9824 from a true straight  
line. The point used as “zero scale” occurs 1/2 LSB before the  
first code transition. “Positive full scale” is defined as a Level 1,  
1/2 LSB beyond the last code transition. The deviation is measured  
from the middle of each particular output code to the true straight  
line. The error is then expressed as a percentage of the 2 V ADC  
full-scale signal. The input signal is always appropriately gained up  
to fill the ADC’s full-scale range.  
Internal Delay for SHP/SHD  
The internal delay (also called aperture delay) is the time delay  
that occurs from when a sampling edge is applied to the AD9824  
until the actual sample of the input signal is held. Both SHP and  
SHD sample the input signal during the transition from low to  
high, so the internal delay is measured from each clock’s rising  
edge to the instant the actual internal sample is taken.  
Total Output Noise  
The rms output noise is measured using histogram techniques.  
The standard deviation of the ADC output codes is calculated  
in LSB and represents the rms noise level of the total signal  
EQUIVALENT INPUT CIRCUITS  
DVDD  
ACVDD  
330ꢁ  
ACVSS  
ACVSS  
DVSS  
Figure 3. CCDIN (Pin 30)  
Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,  
CLPDM, HD, VD, PBLK, SCK, and SL  
DRVDD  
DVDD  
DATA  
DVDD  
DVDD  
DATA IN  
THREE-  
STATE  
330ꢁ  
DOUT  
DATA OUT  
RNW  
DVSS  
DVSS  
DVSS  
DVSS  
DRVSS  
Figure 4. SDATA (Pin 45)  
Figure 2. Data Outputs—D0–D13  
REV. 0  
–7–  

AD9824KCPZRL 替代型号

型号 品牌 替代类型 描述 数据表
AD9824KCPRL ADI

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AD9824KCP ADI

完全替代

Complete 14-Bit 30 MSPS CCD Signal Processor

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