Datasheet > AD9680-500EBZ

AD9680-500EBZ

更新时间： 2022-02-26 09:14:31

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
99页	3113K
描述
Dual Analog-to-Digital Converter

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AD9680-500EBZ 数据手册

AD9680

Data Sheet

GENERAL DESCRIPTION

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/

500 MSPS analog-to-digital converter (ADC). The device has

an on-chip buffer and sample-and-hold circuit designed for low

power, small size, and ease of use. This device is designed for

sampling wide bandwidth analog signals of up to 2 GHz. The

AD9680 is optimized for wide input bandwidth, high sampling

rate, excellent linearity, and low power in a small package.

function in the communications receiver. The programmable

threshold detector allows monitoring of the incoming signal

power using the fast detect output bits of the ADC. If the input

signal level exceeds the programmable threshold, the fast detect

indicator goes high. Because this threshold indicator has low

latency, the user can quickly turn down the system gain to avoid

an overrange condition at the ADC input.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations.

Users can configure the Subclass 1 JESD204B-based high speed

serialized output in a variety of one-, two-, or four-lane

configurations, depending on the DDC configuration and the

acceptable lane rate of the receiving logic device. Multiple device

synchronization is supported through the SYSREF and

SYNCINB input pins.

The analog input and clock signals are differential inputs. Each

ADC data output is internally connected to two digital down-

converters (DDCs). Each DDC consists of up to five cascaded

signal processing stages: a 12-bit frequency translator (NCO),

and four half-band decimation filters. The DDCs are bypassed

by default.

The AD9680 has flexible power-down options that allow

significant power savings when desired. All of these features can

be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.

The AD9680 is available in a Pb-free, 64-lead LFCSP and is

specified over the −40°C to +85°C industrial temperature range.

This product is protected by a U.S. patent.

In addition to the DDC blocks, the AD9680 has several

functions that simplify the automatic gain control (AGC)

Rev. C | Page 4 of 97

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