AD9670
Data Sheet
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, full temperature range (0°C to 85°C), RF decimator bypassed, digital
demodulator and baseband decimator bypassed, unless otherwise noted.
Table 3.
Parameter1
CLOCK2
Temperature Min
Typ
Max
Unit
Clock Rate
40 MSPS (Mode I)
Full
Full
Full
Full
Full
Full
20.5
20.5
20.5
20.5
40
65
80
125
MHz
MHz
MHz
MHz
ns
65 MSPS (Mode II)
80 MSPS (Mode III)3
125 MSPS (Mode IV)4
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS2, 5
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
3.75
3.75
ns
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
10.8 − 1.5 × tDCO
10.8 − 1.5 × tDCO
10.8
300
300
tSAMPLE/7
10.8
tFCO + (tSAMPLE/28)
(tSAMPLE/28)
(tSAMPLE/28)
225
10.8 + 1.5 × tDCO
10.8 + 1.5 × tDCO
ns
ps
ps
ns
ns
ns
ps
ps
ps
ns
ns
Fall Time (tF) (20% to 80%)
6
DCO Period (tDCO
)
FCO Propagation Delay (tFCO
DCO Propagation Delay (tCPD
DCO to Data Delay (tDATA
DCO to FCO Delay (tFRAME
Data-to-Data Skew (tDATA-MAX − tDATA-MIN
TX_TRIG to CLK Setup Time (tSETUP
)
)
7
7
)
(tSAMPLE/28) − 300
(tSAMPLE/28) − 300
(tSAMPLE/28) + 300
(tSAMPLE/28) + 300
400
7
)
)
)
1
1
TX_TRIG to CLK Hold Time (tHOLD
)
Wake-Up Time
Standby
Power-Down
ADC Pipeline Latency
APERTURE
25°C
25°C
Full
2
375
16
ꢀs
ꢀs
Clock cycles
Aperture Uncertainty (Jitter)
LO GENERATION
MLO8 Frequency
4LO Mode
8LO Mode
16LO Mode
RESET9 to MLO Setup Time (tSETUP
RESET to MLO Hold Time (tHOLD
25°C
<1
ps rms
Full
Full
Full
Full
Full
4
8
16
1
1
40
80
160
MHz
MHz
MHz
ns
)
tMLO10/2
tMLO10/2
)
ns
1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and
Evaluation.
2 The clock can be adjusted via the SPI.
3 Mode III must have the RF decimator enabled because the maximum data rate of the baseband demodulator and decimator is 65 MSPS.
4 Mode IV must have the RF decimator enabled because the maximum data rate of the baseband demodulator and decimator is 65 MSPS.
5 Measurements were taken using a device soldered to FR-4 material.
6 In the typical value, tSAMPLE/7, 7 is based on the number of bits (14) divided by 2 because the interface uses double data rate (DDR) sampling.
7 tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
8 MLO refers to the differential signal created via the MLO− pin and the MLO+ pin. This notation is used throughout the data sheet.
9 RESET refers to the differential signal created via the RESET− pin and the RESET+ pin. This notation is used throughout the data sheet.
10 The period of the MLO clock signal is represented by tMLO
.
Rev. A | Page 8 of 52
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