AD9670
Data Sheet
Parameter1
Test Conditions/Comments
Min
Typ
Max
Unit
Two-Tone Intermodulation
Distortion (IMD3)
fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, fLO = 80 MHz,
ARF1 = −1 dBFS, ARF2 = −21 dBFS, IMD3 relative to ARF2
−58
dB
LO Harmonic Rejection
16LO, 8LO, and 4LO modes
I to Q, all phases, 1 σ
I to Q, all phases, 1 σ
Phase I to I, Q to Q, 1 σ
Amplitude I to I, Q to Q, 1 σ
−20
dBc
Degrees
dB
Degrees
dB
Quadrature Phase Error
I/Q Amplitude Imbalance
Channel-to-Channel Matching
0.15
0.015
0.5
0.25
POWER SUPPLY, MODE I/MODE II/
MODE III/MODE IV
AVDD1
AVDD2
DVDD
1.7
2.85
1.3
1.3
1.7
1.8
3.0
1.4
1.8
1.8
1.9
3.6
1.9
1.9
1.9
V
V
V
V
V
mA
Demodulator/decimator enabled
Demodulator/decimator disabled
DRVDD
IAVDD1
TGC mode, LO band mode
148/187/
223/291
CW Doppler mode
4
mA
mA
mA
mA
mA
IAVDD2
TGC mode, no signal, low band mode
TGC mode, no signal, high band mode
CW Doppler mode, 8 channels enabled
RF decimator enabled in Mode III and Mode IV;
demodulator/decimator enabled all modes
230
239
140
156/247/
166/255
IDVDD
IDRVDD
ANSI-644 mode
133/184/
141/146
119/170/
127/169
mA
mA
Low power (IEEE 1596.3 similar) mode, 1 channel per
lane mode
Total Power Dissipation
(Including Output Drivers)
TGC mode, no signal, RF decimator enabled in Mode III
and Mode IV, demodulator/decimator disabled
TGC mode, no signal, RF decimator enabled in Mode III
and Mode IV, demodulator/decimator enabled
1200/1400/
1380/1630
1400/1695/
1570/1900
1345/1555/
1535/2100
1560/1880/
1740/2100
mW
mW
CW Doppler mode, 8 channels enabled
500
mW
mW
mW
Bits
Power-Down Dissipation
Standby Power Dissipation
ADC RESOLUTION
30
50
630
14
ADC REFERENCE
Output Voltage Error
Load Regulation at 1.0 mA
Input Resistance
VREF = 1 V
VREF = 1 V
mV
mV
kΩ
2
7.5
1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation.
2 The overrange condition is specified as 6 dB more than the full-scale input range.
3 The internal LO frequency, fLO, is generated from the supplied multiplier local oscillator frequency, fMLO, by dividing it up by a configurable divider value (M) that can be
4, 8, or 16; the MLO signal is named 4LO, 8LO, or 16LO, accordingly.
Rev. A | Page 6 of 52