AD9600ABCPZ-150

更新时间： 2024-01-29 19:33:38

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
72页	2204K
描述
10-Bit, 105 MSPS/125 MSPS/150 MSPS

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数据手册

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AD9600ABCPZ-150 数据手册

AD9600

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,

DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.

Table 1.

AD9600ABCPZ-105/

AD9600BCPZ-105

AD9600ABCPZ-125/

AD9600BCPZ-125

AD9600ABCPZ-150/

AD9600BCPZ-150

Parameter

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

Full

Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error

Full

25°C

Full

25°C

Guaranteed

±0.3

−2.2

±0.7

−1.0

±0.2

±0.3

−2.5

±0.7

−1.3

±0.2

±0.3

−3.0

±0.7

−1.6

±0.2

% FSR

LSB

−3.6

−4.0

−4.3

Differential Nonlinearity (DNL)¹

±0.1

Integral Nonlinearity (INL)¹

±0.3

±0.4

LSB

MATCHING CHARACTERISTICS

Offset Error

Gain Error

Full

±0.3

±0.2

±0.7

±0.8

±0.3

±0.7

±0.8

±0.2

±0.7

±0.8

% FSR

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

±15

±±5

±15

±±5

±15

±±5

ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode)

Load Regulation @ 1.0 mA

INPUT-REFERRED NOISE

VREF = 1.0 V

Full

±5

±16

±5

±16

±5

±16

25°C

0.1

LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V

Input Capacitance²

VREF INPUT RESISTANCE

POWER SUPPLIES

Full

V p-p

kΩ

Supply Voltage

AVDD, DVDD

DRVDD (CMOS Mode)

Supply Current

Full

1.7

1.8

3.3

1.±

3.6

1.7

1.8

3.3

1.±

3.6

1.7

1.8

3.3

1.±

3.6

Full

310

385

41±

I_AVDD

I_DVDD

1, 3

365

650

455

800

4±5

8±0

I_AVDDand I_DVDD

I_DRVDD(3.3 V CMOS)

I_DRVDD(1.8 V CMOS)

I_DRVDD(1.8 V LVDS)

POWER CONSUMPTION

DC Input

Sine Wave Input¹

DRVDD = 1.8 V

Full

600

750

825

Full

645

740

813

±00

8±2

±±0

DRVDD = 3.3 V

Standby Power³

Power-Down Power

2.5

¹Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

²Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 8 for the equivalent analog input structure.

³Standby power is measured with a dc input and the CLK+ and CLK− pins inactive )set to AVDD or AGND.

Rev. B | Page 5 of 72

1 2 3 456 7 8...72

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