10-Bit, 125/105 MSPS, 1.8 V Dual
Analog-to-Digital Converter (ADC)
AD9608
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
AGND
SDIO SCLK CSB
1.8 V analog supply operation
1.8 V CMOS or 1.8 V LVDS output
SNR = 61.7 dBFS at 70 MHz
SFDR = 85 dBc at 70 MHz
Low power: 71 mW/channel ADC core at 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
SPI
ORA
D9A
PROGRAMMING DATA
VIN+A
VIN–A
ADC
D0A
DCOA
VREF
SENSE
DRVDD
AD9608
DNL = 0.13 LSB
Serial port control options
REF
SELECT
VCM
ORB
D9B
RBIAS
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
VIN–B
VIN+B
ADC
D0B
DCOB
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
DIVIDE
1 TO 8
DUTY CYCLE
STABILIZER
MODE
CONTROLS
CLK+ CLK–
SYNC
DCS
PDWN DFS OEB
NOTES
APPLICATIONS
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FORLVDS PIN NAMES.
Communications
Figure 1.
Diversity radio systems
I/Q demodulation systems
Broadband data applications
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
PRODUCT HIGHLIGHTS
1. Operates from a single 1.8 V analog power supply and
features a separate digital output driver supply to accom-
modate 1.8 V CMOS or 1.8 V LVDS logic families.
2. Provides a patented sample-and-hold circuit that maintains
excellent performance for input frequencies up to 200 MHz
and is designed for low cost, low power, and ease of use.1
3. Includes a standard serial port interface that supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing,
and offset adjustments.
4. Packaged in a 64-lead, RoHS-compliant LFCSP that is pin
compatible with the AD9650, AD9269, and AD9268 16-bit
ADCs, the AD9258 and AD9648 14-bit ADCs, the AD9628
and AD9231 12-bit ADCs, and the AD9204 10-bit ADC,
enabling a simple migration path between 10-bit and 16-bit
converters sampling from 20 MSPS to 125 MSPS.
1 This product is protected by a U.S. patent.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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