Datasheet > 微控制器和处理器 > 时钟发生器> AD9572ACPZLVD-R7

AD9572ACPZLVD-R7

更新时间： 2024-01-14 03:37:11

品牌	Logo	应用领域
亚德诺 - ADI		晶体时钟发生器光纤微控制器和处理器外围集成电路 PC 以太网
页数	文件大小	规格书
20页	410K
描述
Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

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技术参数
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AD9572ACPZLVD-R7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC40,.24SQ,20	针数：	40
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.24
Samacsys Confidence：		Samacsys Status：	Released
Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=578874	PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=578874
Samacsys PartID：	578874	Samacsys Image：	https://componentsearchengine.com/Images/9/AD9572ACPZLVD-R7.jpg
Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/1/AD9572ACPZLVD-R7.jpg	Samacsys Pin Count：	41
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Other
Samacsys Footprint Name：	QFN50P600X600X80-41N	Samacsys Released Date：	2017-01-11 11:21:59
Is Samacsys：	N	JESD-30 代码：	S-XQCC-N40
JESD-609代码：	e3	长度：	6 mm
端子数量：	40	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	156.25 MHz
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC40,.24SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	主时钟/晶体标称频率：	25 MHz
认证状态：	Not Qualified	座面最大高度：	0.8 mm
子类别：	Clock Generators	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	6 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

AD9572ACPZLVD-R7 数据手册

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AD9572

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

Table 15. FREQSEL (Pin 27) Definition

Frequency Available

from Pin 19 and Pin 20

FREQSEL (MHZ)

Frequency Available

from Pin 21 and Pin 22

(MHZ)

The PFD takes inputs from the reference clock and feedback

divider to produce an output proportional to the phase and

frequency difference between them. Figure 15 shows a

simplified schematic.

125

100

125

100

3.3V

CHARGE

PUMP

3.5mA

HIGH

D1 Q1

CLR1

REFCLK

OUT

OUTB

CLR2

D2 Q2

DOWN

3.5mA

HIGH

FEEDBACK

DIVIDER

Figure 13. LVDS Output Simplified Equivalent Circuit

The simplified equivalent circuits of the LVDS and LVPECL

GND

outputs are shown in Figure 13 and Figure 14.

Figure 15. PFD Simplified Schematic

3.3V

POWER SUPPLY

The AD9572 requires a 3.3 V 10ꢀ power supply for V_S. The

tables in the Specifications section give the performance expected

from the AD9572 with the power supply voltage within this

range. The absolute maximum range of −0.3 V to +3.6 V, with

respect to GND, must never be exceeded on the VS pin.

OUT

OUTB

Good engineering practice should be followed in the layout of

power supply traces and the ground plane of the PCB. The

power supply should be bypassed on the PCB with adequate

capacitance (>10 μF). The AD9572 should be bypassed with

adequate capacitors (0.1 μF) at all power pins as close as

possible to the part. The layout of the AD9572 evaluation board

is a good example.

GND

Figure 14. LVPECL Output Simplified Equivalent Circuit

The differential outputs are factory programmed to either LVPECL

or LVDS format, and either option can be sampled on request.

The exposed metal paddle on the AD9572 package is an electrical

connection, as well as a thermal enhancement. For the device to

function properly, the paddle must be properly attached to ground

(GND). The PCB acts as a heat sink for the AD9572; therefore,

this GND connection should provide a good thermal path to a

larger dissipation area, such as a ground plane on the PCB.

CMOS drivers tend to generate more noise than differential

outputs and, as a result, the proximity of the 33.33 MHz output

to Pin 21 and Pin 22 does affect the jitter performance when

FREQSEL = 0 (that is, when the differential output is generating

125 MHz). For this reason, the 33 MHz pin can be forced to a

low state by asserting the FORCE_LOW signal on Pin 37 (see

Table 16). An internal pull-down enables the 33.33 MHz output

if the pin is not connected.

CMOS CLOCK DISTRIBUTION

The AD9572 provides two CMOS clock outputs (one 25 MHz

and one 33.33 MHz) that are dedicated CMOS levels. Whenever

single-ended CMOS clocking is used, some of the following

general guidelines should be followed.

Table 16. FORCE_LOW (Pin 37) Definition

FORCE_LOW

33.33 MHz Output (Pin 23)

0 or NC

33.33 MHz

Point-to-point nets should be designed such that a driver has

one receiver only on the net, if possible. This allows for simple

termination schemes and minimizes ringing due to possible

mismatched impedances on the net. Series termination at the

source is generally required to provide transmission line

matching and/or to reduce current transients at the driver.

Rev. 0 | Page 15 of 20

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与AD9572ACPZLVD-R7相关器件

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AD9572ACPZLVD-RL	ADI	Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs	获取价格
AD9572ACPZPEC	ADI	Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs	获取价格
AD9572ACPZPEC-R7	ADI	Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs	获取价格
AD9572ACPZPEC-RL	ADI	Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs	获取价格
AD9572-EVALZ-LVD	ADI	Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs	获取价格
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