Datasheet > AD9559PCBZ

AD9559PCBZ

更新时间： 2022-06-06 10:15:52

品牌	Logo	应用领域
亚德诺 - ADI		转换器时钟
页数	文件大小	规格书
120页	1688K
描述
Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

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AD9559PCBZ 数据手册

AD9559

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CRYSTAL RESONATOR PATH

Crystal Resonator Frequency Range

Maximum Crystal Motional Resistance

100

MHz

Ω

Fundamental mode, AT cut crystal

REFERENCE INPUTS

Table 5.

Parameter

Min

Max

Unit

Test Conditions/Comments

DIFFERENTIAL OPERATION

Frequency Range

The reference input divide-by-2 block must be engaged

for f_IN> 705 MHz

Sinusoidal Input

LVPECL Input

LVDS Input

Minimum Input Slew Rate

Common-Mode Input Voltage

AC-Coupled

750

1250

750

MHz

V/μs

0.002

Minimum limit imposed for jitter performance

Internally generated

1.9

1.0

2.1

2.4

DC-Coupled

Differential Input Voltage Sensitivity

Minimum differential voltage across pins required to

ensure switching between logic levels; instantaneous

voltage on either pin must not exceed the supply rails

f_IN< 800 MHz

240

320

400

kΩ

f_IN= 800 MHz to 1050 MHz

f_IN= 1050 MHz to 1250 MHz

Differential Input Voltage Hysteresis

Input Resistance

100

Input Capacitance

Minimum Pulse Width High

LVPECL

LVDS

390

640

Minimum Pulse Width Low

LVPECL

LVDS

390

640

SINGLE-ENDED OPERATION

Frequency Range (CMOS)

Minimum Input Slew Rate

Input Voltage High (V_IH)

1.2 V to 1.5 V Threshold Setting

1.8 V to 2.5 V Threshold Setting

3.0 V to 3.3 V Threshold Setting

Input Voltage Low (V_IL)

1.2 V to 1.5 V Threshold Setting

1.8 V to 2.5 V Threshold Setting

3.0 V to 3.3 V Threshold Setting

Input Resistance

0.002

300

MHz

V/μs

Minimum limit imposed for jitter performance

1.0

1.4

2.0

0.35

0.5

1.0

kΩ

Input Capacitance

Minimum Pulse Width High

Minimum Pulse Width Low

1.5

Rev. 0 | Page 6 of 120

1...3 4 567 8 9...120

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