Data Sheet
AD9559
Table 197. Multifunction Pin Input Functions (D7 = 0)
Bits[D7:D0] Value
Output Function
Destination Proxy
0x00
Reserved—high-Z input
None
0x01
0x02
0x03
0x04
0x10
0x11
0x12
0x13
IO_UPDATE
Full power-down
Clear watchdog timer
Sync all channel dividers
Clear all IRQs
Clear common IRQs
Clear DPLL_0 IRQs
Clear DPLL_1 IRQs
Force fault REFA/REFB/REFC/REFD
Force validation timeout REFA/REFB/REFC/REFD
PLL_0 power-down
DPLL_0 user free run
DPLL_0 user holdover
DPLL_0 tuning word history reset
DPLL_0 increment incremental phase offset
DPLL_0 decrement incremental phase offset
DPLL_0 reset incremental phase offset
APLL_0 sync clock distribution outputs
PLL_0 disable all output drivers
PLL_0 disable OUT0A
Register 0x0005, Bit 0
Register 0x0A00, Bit 0
Register 0x0A05, Bit 7
Register 0x0A00, Bit 2
Register 0x0A05, Bit 0
Register 0x0A05, Bit 1
Register 0x0A05, Bit 2
Register 0x0A05, Bit 3
Register 0x0A03, Bits[3:0]
Register 0x0A02, Bits[3:0]
Register 0x0A20, Bit 0
Register 0x0A22, Bit 0
Register 0x0A22, Bit 1
Register 0x0A23, Bit 1
Register 0x0A24, Bit 0
Register 0x0A24, Bit 1
Register 0x0A24, Bit 2
Register 0x0A20, Bit 2
Register 0x0A21, Bits[3:2]
Register 0x0A21, Bit 2
Register 0x0A21, Bit 3
Register 0x0A22, Bit 5
Register 0x0A22, Bit 6
Register 0x0A40, Bit 0
Register 0x0A42, Bit 0
Register 0x0A42, Bit 1
Register 0x0A43, Bit 1
Register 0x0A44, Bit 0
Register 0x0A44, Bit 1
Register 0x0A44, Bit 2
Register 0x0A40, Bit 2
Register 0x0A41, Bits[3:2]
Register 0x0A41, Bit 2
Register 0x0A41, Bit 3
Register 0x0A42, Bit 5
Register 0x0A42, Bit 6
0x20/0x21/0x22/0x23
0x28/0x29/0x2A/0x2B
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E to 0x7F
PLL_0 disable OUT0B
PLL_0 manual reference input selection, Bit 0
PLL_0 manual reference input selection, Bit 1
PLL_1 power-down
DPLL_1 user free run
DPLL_1 user holdover
DPLL_1 tuning word history reset
DPLL_1 increment incremental phase offset
DPLL_1 decrement incremental phase offset
DPLL_1 reset incremental phase offset
APLL_1 sync clock distribution outputs
PLL_1 disable all output drivers
PLL_1 disable OUT1A
PLL_1 disable OUT1B
PLL_1 manual reference input selection, Bit 0
PLL_1 manual reference input selection, Bit 1
Reserved
Rev. 0 | Page 119 of 120