Data Sheet
AD9558
Register Map Bit Descriptions.......................................................73
Reference Inputs (Register 0x0500 to Register 0x0507) ........86
Serial Port Configuration (Register 0x0000 to
Frame Synchronization (Register 0x0640 to
Register 0x0005)..........................................................................73
Register 0x0641)..........................................................................87
Silicon Revision (Register 0x000A) ..........................................73
DPLL Profile Registers (Register 0x0700 to
Register 0x07E6) .........................................................................88
Clock Part Serial ID (Register 0x000C to
Register 0x000D).........................................................................73
Operational Controls (Register 0x0A00 to
Register 0x0A10).........................................................................90
System Clock (Register 0x0100 to Register 0x0108) ..............74
Quick In/Out Frequency Soft Pin Configuration
(Register 0x0C00 to Register 0x0C08) .....................................93
General Configuration (Register 0x0200 to
Register 0x0214)..........................................................................75
Status Readback (Register 0x0D00 to Register 0x0D14).......95
EEPROM Control (Register 0x0E00 to Register 0x0E03) ....... 98
IRQ Mask (Register 0x020A to Register 0x020F)...................76
DPLL Configuration (Register 0x0300 to
Register 0x032E)..........................................................................77
EEPROM Storage Sequence (Register 0x0E10 to
Register 0x0E3C).........................................................................99
Output PLL Configuration (Register 0x0400 to
Register 0x0408)..........................................................................80
Outline Dimensions......................................................................105
Ordering Guide .........................................................................105
Output Clock Distribution (Register 0x0500 to
Register 0x0515)..........................................................................82
REVISION HISTORY
7/2016—Rev. B to Rev. C
Change to Address 0x0101, Table 35............................................62
Changes to Bit 4, Table 43..............................................................73
Updated Outline Dimensions......................................................104
Changes to Features Section, Applications Section, and General
Description Section...........................................................................1
Changes to Table 20 ........................................................................18
Changes to M0 to M6 Pin Description.........................................20
Changes to Figure 33 ......................................................................26
Changes to Device Register Programming Using a Register
Setup File Section ............................................................................27
Added Figure 35 and Figure 36; Renumbered Sequentially......27
Added Figure 37 ..............................................................................28
Changes to DPLL Overview Section and Figure 39 ...................33
Changes to System Clock Details Section....................................37
Added RF Dividers (RF Divider 2 and RF Divider 1) Section.....40
Changes to Control Registers for Frame Synchronization Mode
Section.....................................................................................................42
Changes to Manual EEPROM Download Section and
Automatic EEPROM Download Section .....................................47
Changes to Power Supply Partitions Section and Use of Ferrite
Beads on 1.8 V Supplies Section....................................................60
Added Use of Ferrite Beads on 3.3 V Supplies Section..............60
Changes to Table 35 ........................................................................64
Changes to Read Buffer Register Description, Table 37 ............73
Changes to IRQ Pin Driver Type Description, Table 47............75
Changes to Table 64 ........................................................................80
Changes to Table 66 ........................................................................81
Changes to Table 86 and Table 87 .................................................89
Changes to Status Readback (Register 0x0D00 to Register 0x0D14)
Section and Table 102 .....................................................................95
Changes to Table 110 ......................................................................97
Changes to Table 113 ......................................................................98
4/2012—Rev 0 to Rev. A
Changed 3 Hz to 352 kHz in Output Frequencies List Item,
Features Section.................................................................................1
Change to Output Frequency Range Parameter, Min; and System
Clock Input Doubler Duty Cycle Parameter Description, Table 6 ...6
Changes to Test Conditions/Comments Column, Table 9..........8
Changes to Output Frequency Parameters, Min, Table 10 ..........9
Changes to Pin 4 and Pin 42, Table 20 .........................................17
Changes to Device Register Programming When Using a Register
Setup File and Register Programming Overview Sections.............26
Changed APLL VCO Lower Frequency and OUT5 Frequency
Range, Figure 35; Changed 225 MHz to 200 MHz and 3.45 GHz
to 3.35 GHz in Overview Section ..................................................29
Changes to Reference Profiles Section.........................................30
Changes to Programmable Digital Loop Filter Section.............32
Changes to System Clock Inputs Section.....................................35
Changes to Output PLL (APLL) Section; Changes to Figure 39.....37
Changes to Figure 40; Changed 1024 to 1023 in Clock Dividers
Section; Changes to Clock Distribution Synchronization
Section ..............................................................................................38
Changes to Multifunction Pins (M7 to M0) and IRQ Pin
Sections.............................................................................................42
Changes to Figure 44 ......................................................................43
Changes to EEPROM Conditional Processing Section and
Figure 45...........................................................................................46
Added Programming the EEPROM to Configure an M Pin
to Control Synchronization of Clock Distribution Section .........48
Changes to the Power Supply Partitions Section........................58
Changed 89.5° to 88.5° in DPLL Phase Margin Section............59
6/2013—Rev. A to Rev. B
Changes to Multifunction Pins (M7 to M0) Section..................42
Rev. C | Page 3 of 105
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