Datasheet > AD9550/PCBZ

AD9550/PCBZ

更新时间： 2024-01-21 23:03:53

品牌	Logo	应用领域
亚德诺 - ADI		通信时钟
页数	文件大小	规格书
20页	393K
描述
Integer-N Clock Translator for Wireline Communications

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中文翻译

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技术参数
数据手册

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AD9550/PCBZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC32,.2SQ,20	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.79
应用程序：	SONET;SDH	JESD-30 代码：	S-XQCC-N32
JESD-609代码：	e3	长度：	5 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC32,.2SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	0.8 mm
子类别：	Other Telecom ICs	最大压摆率：	0.185 mA
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	5 mm	Base Number Matches：	1

AD9550/PCBZ 数据手册

AD9550

Loop Filter

DESCRIPTION OF FUNCTIONAL BLOCKS

The charge pump in the PFD delivers current to the loop filter

(see Figure 24). The components primarily responsible for the

bandwidth of the loop filter are external and connect between

Pin 16 and Pin 17.

Input Frequency Prescaler (Divide-by-5)

The divide-by-5 prescaler provides the option to reduce the

input reference frequency by a factor of five. Note that the pre-

scaler physically precedes the ×2 frequency multiplier. This

allows the prescaler to bring a high frequency reference clock

down to a frequency that is within the range of the ×2 frequency

multiplier.

The internal portion of the loop filter has two configurations: one

is for low loop bandwidth applications (~170 Hz) and the other is

for medium (~20 kHz)/high (~75 kHz) bandwidth applications.

The low loop bandwidth condition applies when the feedback

divider value (N) is 2¹⁴(16,384) or greater. Otherwise, the

medium/high loop bandwidth configuration is in effect. The

feedback divider value depends on the configuration of the Ax

and Yx pins per Table 8.

Input ×2 Frequency Multiplier

The ×2 frequency multiplier doubles the frequency at its input,

thereby taking advantage of a higher frequency at the input to

the PLL. This provides greater separation between the frequency

generated by the PLL and the modulation spur associated with

frequency at the PLL input.

AD9550

FROM

CHARGE

PUMP

PLL (PFD, Charge Pump, VCO, Feedback Divider)

375Ω

The PLL (see Figure 23) consists of a phase/frequency detector

(PFD), a partially integrated analog loop filter (see Figure 24),

an integrated voltage controlled oscillator (VCO), and a 20-bit

programmable feedback divider. The PLL generates a 3.35 GHz

to 4.05 GHz clock signal that is phase-locked to the input reference

3kΩ

VCO

400kΩ

53pF

CONTROL

LOGIC

BUFFER

170pF

SWITCHES CHANGE

STATE FOR N ≥ 16384

signal, and its frequency is the phase detector frequency (f_PFD

multiplied by the feedback divider value.

)

FILTER

LDO

The PFD of the PLL drives a charge pump that increases, decreases,

or holds constant the charge stored on the loop filter capacitors

(both internal and external). The stored charge results in a voltage

that sets the output frequency of the VCO. The feedback loop of

the PLL causes the VCO control voltage to vary in such a way as

to phase lock the PFD input signals.

Figure 24. External Loop Filter

The bandwidth of the loop filter primarily depends on three

external components (R, C1, and C2). There are two sets of recom-

mended values for these components corresponding to the low and

medium/high loop bandwidth configurations (see Table 9).

The PLL has a VCO with 128 frequency bands spanning a range

of 3350 MHz to 4050 MHz (3700 MHz nominal). However, the

actual operating frequency within a particular band depends on

the control voltage that appears on the loop filter capacitor.

Table 9. External Loop Filter Components

Loop

The control voltage causes the VCO output frequency to vary

linearly within the selected band. This frequency variability allows

the control loop of the PLL to synchronize the VCO output signal

with the reference signal applied to the PFD. Selection of the VCO

frequency band (as well as gain adjustment) occurs automatically

as part of the automatic VCO calibration process of the device,

which initiates at power-up (or reset). VCO calibration centers

the dc operating point of the VCO control signal. During VCO

calibration, the output drivers provide a static dc signal.

A3 to A0 Pins

0001 to 1100, and 1111

1110¹

Bandwidth

6.8 kΩ 47 nF 1 µF

12 kΩ 51 pF 220 nF 20 kHz

12 kΩ 51 pF 220 nF 75 kHz

0.17 kHz

1101 to 1110

¹The 20 kHz loop bandwidth case only applies when the A3 pin to A0 pin =

1110 and the Y5 pin to Y0 pin = 111111.

To achieve the best jitter performance in applications requiring a

loop bandwidth of less than 1 kHz, C1 and C2 must have an

insulation resistance of at least 500 ΩF.

The feedback divider (N-divider) sets the frequency multiplication

factor of the PLL in integer steps over a 20-bit range. Note that the

N-divider has a lower limit of 32.

PLL Locked Indicator

The PLL provides a status indicator that appears at Pin 20

(LOCKED). When the PLL acquires phase lock, the LOCKED

pin switches to a Logic 1 state. When the PLL loses lock, however,

the LOCKED pin returns to a Logic 0 state.

Rev. 0 | Page 15 of 20

1...12 13 141516 17 18...20

中文翻译

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与AD9550/PCBZ相关器件

型号	品牌	获取价格	描述	数据表
AD9550BCPZ	ADI	获取价格	Integer-N Clock Translator for Wireline Communications
AD9550BCPZ-REEL7	ADI	获取价格	Integer-N Clock Translator for Wireline Communications
AD9551	ADI	获取价格	Multiservice Clock Generator
AD9551/PCBZ	ADI	获取价格	Multiservice Clock Generator
AD9551BCPZ	ADI	获取价格	Multiservice Clock Generator
AD9551BCPZ-REEL7	ADI	获取价格	Multiservice Clock Generator
AD9552	ADI	获取价格	Oscillator Frequency Upconverter
AD9552BCPZ	ADI	获取价格	Oscillator Frequency Upconverter
AD9552BCPZ-REEL7	ADI	获取价格	Oscillator Frequency Upconverter
AD9552PCBZ	ADI	获取价格	Oscillator Frequency Upconverter

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