Datasheet > AD9525BCPZ

AD9525BCPZ

更新时间： 2022-04-18 21:58:03

品牌	Logo	应用领域
亚德诺 - ADI		时钟发生器
页数	文件大小	规格书
48页	1303K
描述
Low Jitter Clock Generator with Eight LVPECL Outputs

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数据手册

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AD9525BCPZ 数据手册

AD9525

Data Sheet

Table 44. LVPECL Drivers OUT5

Reg.

Addr.

(Hex)

Bits Bit Name

Description

0x0F5

[7:5] Don’t care

Don’t care

Reserved

Reserved, write 0

Don’t care

[2:1] OUT5 level

Bit 1 Bit 0 V_OD(mV)

400

600

780 (default)

960

OUT5 driver

power-down

0: enabled (default)

1: power-down

Table 45. LVPECL Drivers OUT6

Reg.

Addr.

(Hex)

Bits Bit Name

Description

0x0F6

[7:5]

Don’t care

Power down

Channel 6 and

Channel 7

Power down Channel 6 and Channel 7

0: enabled (default)

1: power-down

Don’t care

[2:1] OUT6 level

Bit 1 Bit 0 V_OD(mV)

400

600

780 (default)

960

OUT6 driver

power-down

0: enabled (default)

1: power-down

Table 46. LVPECL Drivers OUT7

Reg.

Addr.

(Hex)

Bits Bit Name

Description

0x0F7

[7:5] Don’t care

Don’t care

Reserved

Reserved, write 0

Don’t care

[2:1] OUT7 level

Bit 1 Bit 0 V_OD(mV)

400

600

780 (default)

960

OUT7 driver

power-down

0: enabled (default)

1: power-down

Rev. 0 | Page 42 of 48

1...39 40 414243 44 45...48

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