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AD9520-0BCPZ

更新时间： 2024-02-19 11:17:55
品牌 Logo 应用领域
亚德诺 - ADI 晶体时钟发生器微控制器和处理器外围集成电路
页数 文件大小 规格书
84页 1667K
描述
12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

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AD9520-0BCPZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.64
Is Samacsys：NJESD-30 代码：S-XQCC-N64
JESD-609代码：e3长度：9 mm
湿度敏感等级：3端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：250 MHz封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
主时钟/晶体标称频率：33.33 MHz认证状态：Not Qualified
座面最大高度：1 mm最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：9 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

AD9520-0BCPZ 数据手册

 浏览型号AD9520-0BCPZ的Datasheet PDF文件第78页浏览型号AD9520-0BCPZ的Datasheet PDF文件第79页浏览型号AD9520-0BCPZ的Datasheet PDF文件第80页浏览型号AD9520-0BCPZ的Datasheet PDF文件第81页浏览型号AD9520-0BCPZ的Datasheet PDF文件第82页浏览型号AD9520-0BCPZ的Datasheet PDF文件第84页 
AD9520-0  
Thevenin-equivalent termination uses a resistor network to  
provide 50 Ω termination to a dc voltage that is below VOL of  
the LVPECL driver. In this case, VS_DRV on the AD9520  
should equal VS of the receiving buffer. Although the resistor  
combination shown results in a dc bias point of VS_DRV − 2 V,  
the actual common-mode voltage is VS_DRV − 1.3 V because  
there is additional current flowing from the AD9520 LVPECL  
driver through the pull-down resistor.  
When single-ended CMOS clocking is used, some of the  
following guidelines apply.  
Point-to-point connections should be designed such that each  
driver has only one receiver, if possible. Connecting outputs in  
this manner allows for simple termination schemes and minimizes  
ringing due to possible mismatched impedances on the output  
trace. Series termination at the source is generally required to  
provide transmission line matching and/or to reduce current  
transients at the driver.  
The circuit is identical for the case where VS_DRV = 2.5 V, except  
that the pull-down resistor is 62.5 Ω and the pull-up is 250 Ω.  
VS_DRV  
The value of the resistor is dependent on the board design and  
timing requirements (typically 10 Ω to 100 Ω is used). CMOS  
outputs are also limited in terms of the capacitive load or trace  
length that they can drive. Typically, trace lengths less than  
3 inches are recommended to preserve signal rise/fall times and  
signal integrity.  
VS_DRV  
V
S
127Ω  
127Ω  
50Ω  
SINGLE-ENDED  
(NOT COUPLED)  
LVPECL  
LVPECL  
60.4Ω  
(1.0 INCH)  
50Ω  
10Ω  
CMOS  
CMOS  
83Ω  
83Ω  
MICROSTRIP  
Figure 73. Series Termination of CMOS Output  
Figure 70. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination  
VS_DRV  
V
= VS_DRV  
Termination at the far end of the PCB trace is a second option.  
The CMOS outputs of the AD9520 do not supply enough current  
to provide a full voltage swing with a low impedance resistive, far-  
end termination, as shown in Figure 74. The far-end termination  
network should match the PCB trace impedance and provide the  
desired switching point. The reduced signal swing may still meet  
receiver input requirements in some applications. This can be  
useful when driving long trace lengths on less critical nets.  
S
Z
= 50Ω  
= 50Ω  
0
0
50Ω  
50Ω  
50Ω  
LVPECL  
LVPECL  
Z
Figure 71. DC-Coupled 3.3 V LVPECL Y-Termination  
VS_DRV  
V
S
0.1nF  
V
S
100Ω DIFFERENTIAL  
(COUPLED)  
TRANSMISSION LINE  
100Ω  
LVPECL  
LVPECL  
0.1nF  
100Ω  
100Ω  
50Ω  
10Ω  
CMOS  
CMOS  
200Ω  
200Ω  
Figure 74. CMOS Output with Far-End Termination  
Figure 72. AC-Coupled LVPECL with Parallel Transmission Line  
Because of the limitations of single-ended CMOS clocking,  
consider using differential outputs when driving high speed  
signals over long traces. The AD9520 offers LVPECL outputs  
that are better suited for driving long traces where the inherent  
noise immunity of differential signaling provides superior  
performance for clocking converters.  
CMOS CLOCK DISTRIBUTION  
The output drivers of the AD9520 can be configured as CMOS  
drivers. When selected as a CMOS driver, each output becomes  
a pair of CMOS outputs, each of which can be individually  
turned on or off and set as inverting or noninverting. These  
outputs are 3.3 V or 2.5 V CMOS compatible. However, every  
output driver (including the LVPECL drivers) must be run at  
either 2.5 V or 3.3 V. The user cannot mix and match 2.5 V and  
3.3 V outputs.  
Rev. 0 | Page 83 of 84  
 
 
 
 
 
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