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AD9520-0BCPZ

更新时间： 2024-02-10 20:47:52
品牌 Logo 应用领域
亚德诺 - ADI 晶体时钟发生器微控制器和处理器外围集成电路
页数 文件大小 规格书
84页 1667K
描述
12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

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AD9520-0BCPZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.64
Is Samacsys：NJESD-30 代码：S-XQCC-N64
JESD-609代码：e3长度：9 mm
湿度敏感等级：3端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：250 MHz封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
主时钟/晶体标称频率：33.33 MHz认证状态：Not Qualified
座面最大高度：1 mm最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：9 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

AD9520-0BCPZ 数据手册

 浏览型号AD9520-0BCPZ的Datasheet PDF文件第75页浏览型号AD9520-0BCPZ的Datasheet PDF文件第76页浏览型号AD9520-0BCPZ的Datasheet PDF文件第77页浏览型号AD9520-0BCPZ的Datasheet PDF文件第79页浏览型号AD9520-0BCPZ的Datasheet PDF文件第80页浏览型号AD9520-0BCPZ的Datasheet PDF文件第81页 
AD9520-0  
Reg.  
Addr  
(Hex) Bit(s) Name  
Description  
197  
197  
197  
[6]  
[5]  
[4]  
Divider 2 ignore SYNC  
Divider 2 force high  
Divider 2 start high  
Ignore SYNC.  
[6] = 0; obey chip-level SYNC signal (default).  
[6] = 1; ignore chip-level SYNC signal.  
Forces divider output to high. This requires that ignore SYNC also be set.  
[5] = 0; divider output forced to low (default).  
[5] = 1; divider output forced to high.  
Selects clock output to start high or start low.  
[4] = 0; start low (default).  
[4] = 1; start high.  
197  
198  
[3:0] Divider 2 phase offset  
Phase offset (default: 0x0).  
[2]  
Channel 2 power-down  
Channel 2 powers down.  
[2] = 0; normal operation (default).  
[2] = 1; powered down. (OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 are put into safe power-  
down mode by setting this bit.)  
198  
[1]  
Channel 2 direct-to-output Connects OUT6, OUT7, and OUT8 to Divider 2 or directly to VCO or CLK.  
[1] = 0; OUT6, OUT7, and OUT8 are connected to Divider 2 (default).  
[1] = 1:  
If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT6, OUT7, and OUT8.  
If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT6, OUT7, and OUT8.  
If 0x1E1[1:0] = 01b, there is no effect.  
198  
[0]  
Disable Divider 2 DCC  
Duty-cycle correction function.  
[0] = 0; enable duty-cycle correction (default).  
[0] = 1; disable duty-cycle correction.  
199  
199  
[7:4] Divider 3 low cycles  
[3:0] Divider 3 high cycles  
Number of clock cycles (minus 1) of the divider input during which divider output stays low.  
A value of 0x0 means the divider is low for one input clock cycle (default: 0x0).  
Number of clock cycles (minus 1) of the divider input during which divider output stays high.  
A value of 0x0 means the divider is high for one input clock cycle (default: 0x0).  
19A [7]  
Divider 3 bypass  
Bypasses and powers down the divider; routes input to divider output.  
[7] = 0; use divider (default).  
[7] = 1; bypass divider.  
19A  
19A  
[6]  
[5]  
Divider 3 ignore SYNC  
Divider 3 force high  
Divider 3 start high  
Ignore SYNC.  
[6] = 0; obey chip-level SYNC signal (default).  
[6] = 1; ignore chip-level SYNC signal.  
Forces divider output to high. This requires that ignore SYNC also be set.  
[5] = 0; divider output forced to low (default).  
[5] = 1; divider output forced to high.  
Selects clock output to start high or start low.  
[4] = 0; start low (default).  
19A [4]  
[4] = 1; start high.  
19A [3:0] Divider 3 phase offset  
19B [2] Channel 3 power-down  
Phase offset (default: 0x0).  
Channel 3 powers down.  
[2] = 0; normal operation (default).  
[2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are also put into  
safe power-down mode by setting this bit.)  
Rev. 0 | Page 78 of 84  
1...75767778798081...84

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