Datasheet > AD9518-4BCPZ

AD9518-4BCPZ

更新时间： 2024-01-26 07:34:46

品牌	Logo	应用领域
亚德诺 - ADI		驱动逻辑集成电路
页数	文件大小	规格书
64页	757K
描述
6-Output Clock Generator with Integrated 1.6 GHz VCO

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AD9518-4BCPZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	48
Reach Compliance Code：	unknown	风险等级：	5.67
系列：	9518	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-XQCC-N48	JESD-609代码：	e3
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	6	功能数量：	1
反相输出次数：		端子数量：	48
实输出次数：	6	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	240
传播延迟（tpd）：	1.18 ns	认证状态：	COMMERCIAL
Same Edge Skew-Max（tskwd）：	0.22 ns	座面最大高度：	1 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm	最小 fmax：	2950 MHz
Base Number Matches：	1

AD9518-4BCPZ 数据手册

AD9518-4

APPLICATIONS INFORMATION

Considering an ideal ADC of infinite resolution where the step

size and quantization error can be ignored, the available SNR

can be expressed approximately by

FREQUENCY PLANNING USING THE AD9518

The AD9518 is a highly flexible PLL. When choosing the PLL

settings and version of the AD9518, keep in mind the following

guidelines.

⎛

⎜

⎝

⎞

⎟

⎠

SNR(dB) = 20×log

2πf_At_J

The AD9518 has the following four frequency dividers: the

reference (or R) divider, the feedback (or N) divider, the VCO

divider, and the channel divider. When trying to achieve a

particularly difficult frequency divide ratio requiring a large

amount of frequency division, some of the frequency division

can be done by either the VCO divider or the channel divider,

thus allowing a higher phase detector frequency and more

flexibility in choosing the loop bandwidth.

where:

f_Ais the highest analog frequency being digitized.

t_Jis the rms jitter on the sampling clock.

Figure 51 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

110

SNR = 20log

2πf_At_J

100

Within the AD9518 family, lower VCO frequencies generally

result in slightly lower jitter. The difference in integrated jitter

(from 12 kHz to 20 MHz offset) for the same output frequency is

usually less than 150 fs over the entire VCO frequency range

(1.45 GHz to 2.95 GHz) of the AD9518 family. If the desired

frequency plan can be achieved with a version of the AD9518

that has a lower VCO frequency, choosing the lower frequency

part results in the lowest phase noise and the lowest jitter.

However, choosing a higher VCO frequency may result in more

flexibility in frequency planning.

Choosing a nominal charge pump current in the middle of the

allowable range as a starting point allows the designer to increase or

decrease the charge pump current and, thus, allows the designer

to fine-tune the PLL loop bandwidth in either direction.

100

f_A(MHz)

Figure 51. SNR and ENOB vs. Analog Input Frequency

For more information, see the AN-756 Application Note, Sampled

Systems and the Effects of Clock Phase Noise and Jitter; and the

AN-501 Application Note, Aperture Uncertainty and ADC System

Performance, at www.analog.com.

ADIsimCLK is a powerful PLL modeling tool that can be

downloaded from www.analog.com. It is very accurate in

determining the optimal loop filter for a given application.

USING THE AD9518 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. (Distributing a single-ended clock on a noisy PCB

may result in coupled noise on the sample clock. Differential

distribution has inherent common-mode rejection that can provide

superior clock performance in a noisy environment.) The AD9518

features LVPECL outputs that provide differential clock outputs,

which enable clock solutions that maximize converter SNR

performance. The input requirements of the ADC (differential

or single-ended, logic level, termination) should be considered

when selecting the best clocking/converter solution.

Any high speed ADC is extremely sensitive to the quality of its

sampling clock. An ADC can be thought of as a sampling mixer,

and any noise, distortion, or timing jitter on the clock is combined

with the desired signal at the analog-to-digital output. Clock

integrity requirements scale with the analog input frequency

and resolution, with higher analog input frequency applications

at ≥14-bit resolution being the most stringent. The theoretical

SNR of an ADC is limited by the ADC resolution and the jitter

on the sampling clock.

Rev. A | Page 60 of 64

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AD9518-4BCPZ 替代型号

型号	品牌	替代类型	描述	数据表
AD9518-4ABCPZ-RL7	ADI	功能相似	6-Output Clock Generator with Integrated 1.6 GHz VCO

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AD9520-0BCPZ	ADI	12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO	获取价格
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