AD9518-4

更新时间： 2024-01-04 22:57:10

品牌	Logo	应用领域
亚德诺 - ADI		时钟发生器
页数	文件大小	规格书
64页	985K
描述
6-Output Clock Generator with Integrated 1.6 GHz VCO

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD9518-4 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	48
Reach Compliance Code：	unknown	风险等级：	5.67
系列：	9518	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-XQCC-N48	JESD-609代码：	e3
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	6	功能数量：	1
反相输出次数：		端子数量：	48
实输出次数：	6	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	240
传播延迟（tpd）：	1.18 ns	认证状态：	COMMERCIAL
Same Edge Skew-Max（tskwd）：	0.22 ns	座面最大高度：	1 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm	最小 fmax：	2950 MHz
Base Number Matches：	1

AD9518-4 数据手册

AD9518-4

Data Sheet

Reg.

Addr

(Hex) Bits

Name

Description

0x1E1

Power down clock input section

Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).

0: normal operation (default).

1: power-down.

Power down VCO clock interface

Power down VCO and CLK

Select VCO or CLK

Powers down the interface block between VCO and clock distribution.

0: normal operation (default).

1: power-down.

Powers down both VCO and CLK input.

0; normal operation (default).

1: power-down.

Selects either the VCO or the CLK as the input to VCO divider.

0: selects external CLK as input to VCO divider (default).

1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.

Bypasses or uses the VCO divider.

Bypass VCO divider

0: uses VCO divider (default).

1: bypasses VCO divider; cannot select VCO as input when this is selected.

Table 48. System

Reg.

Addr.

(Hex) Bits

Name

Description

0x230

Power down SYNC

Powers down the sync function.

0: normal operation of the sync function (default).

1: powers down sync circuitry.

Power down distribution

reference

Powers down the reference for distribution section.

0: normal operation of the reference for the distribution section (default).

1: powers down the reference for the distribution section.

Soft sync

The soft sync bit works the same as the SYNC pin, except that the polarity of the bit

is reversed. That is, a high level forces selected channels into a predetermined static

state, and a 1-to-0 transition triggers a sync.

0: same as SYNC high (default).

1: same as SYNC low.

Table 49. Update All Registers

Reg.

Addr

(Hex) Bits

Name

Description

0x232

Update all registers

This bit must be set to 1b to transfer the contents of the buffer registers into the active

registers, which happens on the next SCLK rising edge. This bit is self-clearing; that is,

it does not have to be set back to 0b.

1 (self-clearing): updates all active registers to the contents of the buffer registers.

Rev. B | Page 58 of 64

1...55 56 575859 60 61...64

下载PDF

与AD9518-4相关器件

型号	品牌	描述	获取价格	数据表
AD9518-4ABCPZ	ADI	6-Output Clock Generator with Integrated 1.6 GHz VCO	获取价格
AD9518-4ABCPZ-RL7	ADI	6-Output Clock Generator with Integrated 1.6 GHz VCO	获取价格
AD9518-4A-PCBZ	ADI	6-Output Clock Generator with Integrated 1.6 GHz VCO	获取价格
AD9518-4BCPZ	ADI	6-Output Clock Generator with Integrated 1.6 GHz VCO	获取价格
AD9518-4BCPZ-REEL7	ADI	6-Output Clock Generator with Integrated 1.6 GHz VCO	获取价格
AD9520	ADI	Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers	获取价格

与AD9518-4相关文章

深入解析CS8416引脚说明、参数、技术特点
2024-06-03

1
TPA3116D2功放芯片参数详解、引脚说明
2024-06-03

1
移位寄存器74HC165引脚说明、驱动程序示例解读
2024-06-03

2
深入解析AD9833：DDS频率合成器的卓越性能与广泛应用
2024-06-03

2

产品中心

服务支持

精选活动

关于我们

帮助中心

AD9518-4

AD9518-4 技术参数

AD9518-4 数据手册

与AD9518-4相关器件

与AD9518-4相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD9518-4

AD9518-4 技术参数

AD9518-4 数据手册

与AD9518-4相关器件

与AD9518-4相关文章

您还可以找

您在本页遇到什么问题？