Datasheet > AD9387NK/PCB

AD9387NK/PCB

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
12页	286K
描述
High Performance, Low Power HDMI⑩/DVI Transmitter

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AD9387NK/PCB 数据手册

Preliminary Technical Data

AD9387NK

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

DVDD

HSYNC

VSYNC

CLK

48 DVDD

47 D15

46 D16

45 D17

44 D18

43 D19

42 D20

41 D21

40 D22

S/PDIF

MCLK

AD9387NK

I S0

TOP VIEW

(Not to Scale)

I S1 10

39 D23

I S2 11

38 MCL

37 MDA

36 SDA

35 SCL

34 DDCSDA

33 DDCSCL

I S3 12

10 9

8 7 6 5 4 3 2 1

SCLK 13

LRCLK 14

PVDD 15

PVDD 16

BOTTOM VIEW

(Not to Scale)

NOTES

1. GND PADDLE ON BOTTOM OF PACKAGE.

Figure 3. 76-Ball BGA Configuration (Top View)

Figure 2. 64-Lead LFCSP Pin Configuration (Top View)

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Type¹

Description

BGA

LFCSP

A1 to A10,

B1 to B10, C9,

C10, D9, D10

39 to 47,

50 to 63, 2

D[23:0]

Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels

from 1.8 V to 3.3 V.

CLK

HSYNC

VSYNC

EXT_SWG

Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.

Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this

pin and ground.

HPD

Hot Plug Detect Signal. This indicates to the interface if the receiver is

connected. Supports CMOS logic levels from 1.8 V to 5.0 V.

S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a

Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.

S/PDIF

MCLK

Audio Reference Clock. 128 × N × f_Swith N = 1, 2, 3, or 4. Set to 128 × sampling

frequency (f_S), 256 × f_S, 384 × f_S, or 512 × f_S. Supports CMOS logic levels from 1.8

V to 3.3 V.

F2, F1, G2, G1

9 to 12

I²S[3:0]

I²S Audio Data Inputs. These represent the eight channels of audio (two per

input) available through I²S. Supports CMOS logic levels from 1.8 V to 3.3 V.

SCLK

LRCLK

PD/A0

I²S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.

Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.

Power-Down Control and I²C Address Selection. The I²C address and the PD

polarity are set by the PD/A0 pin state when the supplies are applied to the

AD9387NK. Supports CMOS logic levels from 1.8 V to 3.3 V.

K1, K2

21, 22

30, 31

TxC−/TxC+

Tx2−/Tx2+

Differential Clock Output. Differential clock output at pixel clock rate; TMDS

logic level.

Differential Output Channel 2. Differential output of the red data at 10× the pixel

clock rate; TMDS logic level.

K10, J10

Rev. PrA | Page 5 of 12

1 2 3 456 7 8...12

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