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AD8403AR1

更新时间： 2024-01-26 10:19:09
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器数字电位计电阻器光电二极管
页数 文件大小 规格书
20页 497K
描述
1-/2-/4-Channel Digital Potentiometers

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中文翻译

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AD8403AR1 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：24
Reach Compliance Code：unknown风险等级：5.77
Is Samacsys：N其他特性：IT CAN ALSO OPERATE FROM A 5V NOMINAL SUPPLY
标称带宽：5 kHz控制接口：3-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G24
JESD-609代码：e0长度：15.4 mm
湿度敏感等级：3功能数量：4
位置数：256端子数量：24
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：240认证状态：COMMERCIAL
电阻定律：LINEAR最大电阻器端电压：5.5 V
最小电阻器端电压：座面最大高度：2.65 mm
标称供电电压：3 V表面贴装：YES
标称温度系数：700 ppm/ °C温度等级：AUTOMOTIVE
端子面层：TIN LEAD端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30标称总电阻：1000 Ω
宽度：7.5 mmBase Number Matches：1

AD8403AR1 数据手册

 浏览型号AD8403AR1的Datasheet PDF文件第11页浏览型号AD8403AR1的Datasheet PDF文件第12页浏览型号AD8403AR1的Datasheet PDF文件第13页浏览型号AD8403AR1的Datasheet PDF文件第15页浏览型号AD8403AR1的Datasheet PDF文件第16页浏览型号AD8403AR1的Datasheet PDF文件第17页 
AD8400/AD8402/AD8403  
Table II. Input Logic Control Truth Table  
AD8403  
RDAC 1  
RDAC 2  
CS  
ADDR  
DECODE  
CLK CS RS SHDN Register Activity  
RDAC 4  
L
P
L
L
H
H
H
H
No SR effect, enables SDO pin.  
CLK  
SDI  
SERIAL  
REGISTER  
Shift One bit in from the SDI pin.  
The tenth previously entered bit is  
shifted out of the SDO pin.  
X
P
H
H
Load SR data into RDAC latch  
based on A1, A0 decode (Table III).  
Figure 39. Equivalent Input Control Logic  
The target RDAC latch is loaded with the last eight bits of the  
serial data word completing one DAC update. In the case of the  
AD8403 four separate 10-bit data words must be clocked in to  
change all four VR settings.  
X
X
H
X
H
L
H
H
No Operation.  
Sets all RDAC latches to midscale,  
wiper centered, and SDO latch  
cleared.  
SHDN  
X
X
H
H
P
H
L
Latches all RDAC latches to 80H.  
CS  
SDO  
H
Open circuits all resistor  
SERIAL  
REGISTER  
A–terminals, connects W to B,  
turns off SDO output transistor.  
SDI  
D
Q
RS  
CK  
CLK  
NOTE: P = positive edge, X = don’t care, SR = shift register.  
RS  
The serial data-output (SDO) pin contains an open drain n-  
channel FET. This output requires a pull-up resistor in order to  
transfer data to the next package’s SDI pin. The pull-up resistor  
termination voltage may be larger than the VDD supply (but less  
than max VDD of +8 V) of the AD8403 SDO output device,  
e.g., the AD8403 could operate at VDD = 3.3 V and the pull-up  
for interface to the next device could be set at +5 V. This allows  
for daisy chaining several RDACs from a single processor serial  
data line. The clock period needs to be increased when using a  
pull-up resistor to the SDI pin of the following device in the  
series. Capacitive loading at the daisy chain node SDO–SDI  
between devices must be accounted for to successfully transfer  
data. When daisy chaining is used, the CS should be kept low  
until all the bits of every package are clocked into their respec-  
tive serial registers insuring that the address bits and data bits  
are in the proper decoding location. This would require 20 bits  
of address and data complying to the word format provided in  
Table I if two AD8403 four-channel RDACs are daisy chained.  
Note, only the AD8403 has a SDO pin. During shutdown  
SHDN the SDO output pin is forced to the off (logic high state)  
to disable power dissipation in the pull up resistor. See Figure 40  
for equivalent SDO output circuit schematic.  
Figure 40. Detail SDO Output Schematic of the AD8403  
All digital pins are protected with a series input resistor and par-  
allel Zener ESD structure shown in Figure 41a. This structure  
applies to digital pins CS, SDI, SDO, RS, SHDN, CLK. The  
digital input ESD protection allows for mixed power supply  
applications where +5 V CMOS logic can be used to drive an  
AD8400/AD8402 or AD8403 operating from a +3 V power sup-  
ply. The analog pins A, B, W are protected with a 20 Ω series  
resistor and parallel Zener, see Figure 41b.  
1kΩ  
DIGITAL  
LOGIC  
PINS  
Figure 41a. Equivalent ESD Protection Circuits  
20Ω  
A, B, W  
The data setup and data hold times in the specification table de-  
termine the data valid time requirements. The last 10 bits of the  
data word entered into the serial register are held when CS re-  
turns high. At the same time CS goes high it gates the address  
decoder, which enables one of the two (AD8402) or four  
(AD8403) positive edge triggered RDAC latches. See Figure 39  
detail and Table III Address Decode Table.  
Figure 41b. Equivalent ESD Protection Circuit (Analog  
Pins)  
RDAC  
10kΩ  
A
B
C
C
A
B
C
W
120pF  
Table III. Address Decode Table  
DW  
256  
DW  
256  
C
= 90.4pF · (1 –  
) + 30pF  
C
= 90.4pF · (  
) + 30pF  
B
A
A1  
A0  
Latch Decoded  
W
0
0
1
1
0
1
0
1
RDAC#1  
RDAC#2  
RDAC#3 AD8403 Only  
RDAC#4 AD8403 Only  
Figure 42. RDAC Circuit Simulation Model for RDAC =  
10 kΩ  
–14–  
REV. B  
1...11121314151617...20

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AD8403AR1 替代型号

型号 品牌 替代类型 描述 数据表
AD8403AR1 ADI

当前型号

 1-/2-/4-Channel Digital Potentiometers
AD8403ARZ1 ADI

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