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AD8403ARU100 PDF预览

AD8403ARU100

更新时间: 2024-11-26 22:50:03
品牌 Logo 应用领域
亚德诺 - ADI 转换器电位器数字电位计
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20页 497K
描述
1-/2-/4-Channel Digital Potentiometers

AD8403ARU100 数据手册

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1-/2-/4-Channel  
Digital Potentiometers  
a
AD8400/AD8402/AD8403  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
256 Position  
Replaces 1, 2 or 4 Potentiometers  
1 k, 10 k, 50 k, 100 k⍀  
Power Shut Down—Less than 5 A  
3-Wire SPI Compatible Serial Data Input  
10 MHz Update Data Loading Rate  
+2.7 V to +5.5 V Single-Supply Operation  
Midscale Preset  
RDAC1  
8
A1  
W1  
B1  
8-BIT  
LATCH  
AD8403  
V
DD  
CK  
SHDN  
RS  
AGND1  
DGND  
1
2
3
4
DAC  
SELECT  
RDAC2  
8
A2  
8-BIT  
LATCH  
W2  
B2  
A1, A0  
2
CK  
RS  
SHDN  
AGND2  
APPLICATIONS  
RDAC3  
8
Mechanical Potentiometer Replacement  
Programmable Filters, Delays, Time Constants  
Volume Control, Panning  
Line Impedance Matching  
Power Supply Adjustment  
A3  
8
8
10-BIT  
SERIAL  
LATCH  
8-BIT  
LATCH  
W3  
B3  
CK  
SHDN  
RS  
AGND3  
D
SDI  
CLK  
CS  
CK  
Q
RS  
RDAC4  
A4  
8-BIT  
LATCH  
W4  
B4  
GENERAL DESCRIPTION  
CK  
SHDN  
SHDN  
RS  
AGND4  
The AD8400/AD8402/AD8403 provide a single, dual or quad  
channel, 256 position digitally controlled variable resistor (VR)  
device. These devices perform the same electronic adjustment  
function as a potentiometer or variable resistor. The AD8400  
contains a single variable resistor in the compact SO-8 package.  
The AD8402 contains two independent variable resistors in  
space saving SO-14 surface mount package. The AD8403 con-  
tains four independent variable resistors in 24-lead PDIP, SOIC  
and TSSOP packages. Each part contains a fixed resistor with a  
wiper contact that taps the fixed resistor value at a point deter-  
mined by a digital code loaded into the controlling serial input  
register. The resistance between the wiper and either endpoint  
of the fixed resistor varies linearly with respect to the digital  
code transferred into the VR latch. Each variable resistor offers  
a completely programmable value of resistance, between the A  
terminal and the wiper or the B terminal and the wiper. The  
fixed A to B terminal resistance of 1 k, 10 k, 50 kor 100 kΩ  
has a ±1% channel-to-channel matching tolerance with a nominal  
temperature coefficient of 500 ppm/°C. A unique switching cir-  
cuit minimizes the high glitch inherent in traditional switched  
resistor designs avoiding any make-before-break or break-before-  
make operation.  
SDO  
RS  
The reset (RS) pin forces the wiper to the midscale position by  
loading 80H into the VR latch. The SHDN pin forces the resis-  
tor to an end-to-end open circuit condition on the A terminal  
and shorts the wiper to the B terminal, achieving a microwatt  
power shutdown state. When SHDN is returned to logic high,  
the previous latch settings put the wiper in the same resistance  
setting prior to shutdown. The digital interface is still active in  
shutdown so that code changes can be made which will produce  
new wiper positions when the device is taken out of shutdown.  
The AD8400 is available in both the SO-8 surface mount and  
the 8-lead plastic DIP package.  
The AD8402 is available in both surface mount (SO-14) and  
the 14-lead plastic DIP package, while the AD8403 is available  
in a narrow body 24-lead plastic DIP and the 24-lead surface  
mount package. The AD8402/AD8403 are also offered in the  
1.1 mm thin TSSOP-14/TSSOP-24 package for PCMCIA ap-  
plications. All parts are guaranteed to operate over the extended  
industrial temperature range of –40°C to +85°C.  
Each VR has its own VR latch that holds its programmed  
resistance value. These VR latches are updated from an SPI  
compatible serial-to-parallel shift register that is loaded from a  
standard 3-wire serial-input digital interface. Ten data bits make  
up the data word clocked into the serial input register. The data  
word is decoded where the first two bits determine the address  
of the VR latch to be loaded, the last eight bits are data. A serial  
data output pin at the opposite end of the serial register allows  
simple daisy-chaining in multiple VR applications without addi-  
tional external decoding logic.  
REV. B  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 617/329-4700  
Fax: 617/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1997  

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