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AD8390A

更新时间： 2024-01-18 08:42:38
品牌 Logo 应用领域
亚德诺 - ADI 放大器
页数 文件大小 规格书
12页 387K
描述
Low Power, High Output Current Differential Amplifier

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AD8390A 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：HSSOP,针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.33.00.01风险等级：5.68
放大器类型：OPERATIONAL AMPLIFIER最大平均偏置电流 (IIB)：7 µA
标称共模抑制比：64 dB最大输入失调电压：3000 µV
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：4.9 mm湿度敏感等级：3
负供电电压上限：-13.2 V标称负供电电压 (Vsup)：-5 V
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, HEAT SINK/SLUG, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.75 mm标称压摆率：300 V/us
子类别：Operational Amplifier供电电压上限：13.2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3.9 mmBase Number Matches：1

AD8390A 数据手册

 浏览型号AD8390A的Datasheet PDF文件第6页浏览型号AD8390A的Datasheet PDF文件第7页浏览型号AD8390A的Datasheet PDF文件第8页浏览型号AD8390A的Datasheet PDF文件第9页浏览型号AD8390A的Datasheet PDF文件第11页浏览型号AD8390A的Datasheet PDF文件第12页 
AD8390A  
Data Sheet  
APPLICATIONS INFORMATION  
POWER MANAGEMENT  
SUPPLIES, GROUNDING, AND LAYOUT  
The AD8390A offers significant versatility for maximizing  
efficiency while maintaining optimal levels of performance.  
The AD8390A can be powered from either single or dual  
supplies, with the total supply voltage ranging from 10 V to  
24 V. For optimum performance, use well-regulated low ripple  
supplies.  
Optimizing driver efficiency while delivering the required signal  
level is accomplished with two on-chip power management  
features: two PD pins to select one of four bias modes and an  
As with all high speed amplifiers, pay close attention to supply  
decoupling, grounding, and overall board layout. Provide low  
frequency supply decoupling with 10 µF tantalum capacitors  
from each supply to ground. In addition, decouple all supply  
pins with 0.1 µF quality ceramic chip capacitors placed as close  
as possible to the driver. Use an internal low impedance ground  
plane to provide a common ground point for all driver and  
decoupling capacitor ground requirements. Whenever possible,  
use separate ground planes for analog and digital circuitry.  
I
ADJ pin for fine bias adjustments.  
PD(1:0) Pins  
Two CMOS-compatible logic pins, PD1 and PD0, select one of  
three active power levels and a power-down mode.  
The digital ground pin (DGND) is the logic ground reference  
for the PD(1:0) pins. PD(1:0) = (0,0) is the power-down mode.  
The PD pins are internally connected to DGND via termination  
resistors. When the PD pins are left unconnected, the AD8390A  
is in power-down mode.  
Follow high speed layout techniques to minimize parasitic  
capacitance around the inverting inputs. Some practical  
examples of these techniques are keeping feedback traces as  
short as possible and clearing away ground plane in the area of  
the inverting inputs.  
The AD8390A exhibits a low output impedance in the three  
active modes. The output impedance in the power-down mode  
is high but undefined and may not be suitable for systems that  
rely on a high impedance OFF state, such as multiplexing.  
Keep input and output traces as short as possible and as far  
apart from each other as practical to minimize crosstalk. Keep  
all differential signal traces as symmetrical as possible.  
IADJ Pin  
The IADJ pin provides bias current fine-tuning.  
VCOM PIN  
With the IADJ pin unconnected, the bias currents are internally  
set to 10 mA, 6.7 mA, and 3.8 mA for the three active modes.  
By design, the VCOM pin is internally biased at midsupply,  
eliminating the need for external resistors. However, the  
designer may set VCOM to other voltage levels with an external  
low impedance source.  
With the IADJ pin connected to the negative supply (VEE), the  
bias currents are reduced by approximately 50%.  
A resistor, RADJ, connected between the IADJ pin and the negative  
supply, provides fine bias adjustment as shown in Figure 8.  
When the VCOM pin is left unconnected, decouple it with a  
0.1 µF capacitor to ground, placed in close proximity to the  
AD8390A.  
Table 5. PD and IADJ Selection Guide  
PD1  
1
PD0  
1
RADJ (Ω)  
IQ (mA)  
10.0  
6.7  
With dual equal supplies, connect the VCOM pin directly to  
ground to bias the outputs at midsupply, eliminating the need  
for the external decoupling capacitor.  
∞
∞
∞
∞
0
1
0
0
1
3.8  
0
0
0.67  
5.5  
1
1
1
0
0
4.0  
0
1
0
2.6  
0
0
0
0.56  
Rev. B | Page 10 of 12  
 
 
 
 
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