5秒后页面跳转
捷配首页

Datasheet > 驱动程序和接口 > 显示驱动器> AD8383ACPZ
AD8383ACPZ PDF预览

AD8383ACPZ

更新时间： 2024-01-30 02:30:19
品牌 Logo 应用领域
亚德诺 - ADI 显示驱动器驱动程序和接口接口集成电路
页数 文件大小 规格书
16页 474K
描述
Low Cost 10-Bit, 6-Channel Output Decimating LCD DecDriver

阅读下载

中文翻译

获取价格

AD8383ACPZ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：7 X 7 MM, 0.85 MM HEIGHT, MO-220VKKD-2, LFCSP-48针数：48
Reach Compliance Code：unknown风险等级：5.75
Is Samacsys：N数据输入模式：PARALLEL
接口集成电路类型：LIQUID CRYSTAL DISPLAY DRIVERJESD-30 代码：S-XQCC-N48
JESD-609代码：e3长度：7 mm
湿度敏感等级：3复用显示功能：NO
功能数量：1区段数：6
端子数量：48最高工作温度：75 °C
最低工作温度：封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL座面最大高度：1 mm
标称供电电压：3.3 V电源电压1-Nom：15.5 V
表面贴装：YES温度等级：COMMERCIAL EXTENDED
端子面层：MATTE TIN端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：7 mm
Base Number Matches：1

AD8383ACPZ 数据手册

 浏览型号AD8383ACPZ的Datasheet PDF文件第7页浏览型号AD8383ACPZ的Datasheet PDF文件第8页浏览型号AD8383ACPZ的Datasheet PDF文件第9页浏览型号AD8383ACPZ的Datasheet PDF文件第11页浏览型号AD8383ACPZ的Datasheet PDF文件第12页浏览型号AD8383ACPZ的Datasheet PDF文件第13页 
AD8383  
PCB DESIGN FOR GOOD THERMAL PERFORMANCE  
THERMAL PAD DESIGN  
The total maximum power dissipation of the AD8383 is partly  
dependent on load. In a 6-channel 60 Hz XGA system running  
at a 65 MHz clock rate, the total maximum power dissipation is  
1.08 W at an LCD panel input capacitance of 150 pF.  
Thermal performance of the AD8383 varies logarithmically  
with the contact area between the exposed thermal paddle and  
the thermal pad on the top layer of the PCB. See Figure 11.  
The θJA (of the AD8383 mounted on a standard JEDEC PCB) is  
reduced by approximately 40% as the contact area increases  
from 0% (no thermal pad) to 50%. It approaches its specified  
value as the contact area (on the JEDEC standard PCB)  
approaches 100%.  
At the maximum specified clock rate of 100 Ms/s, the total  
maximum power dissipation can exceed 2 W for large capacitive  
loads, as shown in Table 4.  
Although the maximum safe operating junction temperature is  
higher, the AD8383 is 100% tested at a junction temperature of  
125°C. Consequently, the maximum guaranteed operating  
junction temperature is 125°C. To limit the maximum junction  
temperature at or below the guaranteed maximum, the package,  
in conjunction with the PCB, must effectively conduct heat  
away from the junction.  
In order to minimize thermal performance degradation of  
production PCBs, the contact area between the thermal pad and  
the PCB should be maximized. Therefore, the size of the  
thermal pad should match the exposed 5.25 mm × 5.25 mm  
paddle size. However, if the PCB design rules require a pad-to-  
pad clearance of more than 0.3 mm, the size of the thermal pad  
may be reduced to 5 mm × 5 mm. Additionally, a second  
thermal pad of the same size should be placed on the bottom  
side of the PCB. At least one thermal pad should be in direct  
thermal (and electrical) contact with the AVCC plane.  
The AD8383’s LFCSP package is designed to provide superior  
thermal characteristics, partly achieved by an exposed die  
paddle on the bottom surface of the package. In order to take  
full advantage of this feature, the exposed paddle must be in  
direct thermal contact with the PCB, which then serves as a  
heat sink.  
50  
45  
40  
35  
30  
25  
A thermally effective PCB must incorporate a thermal pad and  
a thermal via structure. The thermal pad provides a solderable  
contact surface on the top surface of the PCB. The thermal via  
structure provides a thermal path to the inner and bottom  
layers of the PCB to remove heat.  
0
25  
50  
75  
100  
CONTACT AREA (%)  
Figure 11. Thermal Performance vs. Contact Area (on a JEDEC PCB)  
Table 4. Power Dissipation vs. Load Capacitance and VFS at 100 Ms/s Clock Rate  
VFS = 5 V  
VFS = 4 V  
PTOTAL (W)  
CLOAD (pF)  
150  
200  
250  
300  
PQUIESCENT (W)  
PDYNAMIC (W)  
0.72  
0.96  
1.20  
1.44  
PTOTAL (W)  
1.42  
1.66  
1.90  
2.14  
PDYNAMIC (W)  
0.58  
0.77  
0.96  
1.15  
0.7  
0.7  
0.7  
0.7  
1.28  
1.47  
1.66  
1.85  
Rev. 0 | Page 10 of 16  
 
 
 
1...78910111213...16

中文翻译

下载PDF

与AD8383ACPZ相关器件

型号 品牌 描述 获取价格 数据表
AD8384 ADI 10-Bit, 6-Channel Decimating LCD DecDriver-R with Level Shifters

获取价格
AD8384ASVZ ADI 10-Bit, 6-Channel Decimating LCD DecDriver-R with Level Shifters

获取价格
AD8385 ADI 10-Bit, 12-Channel Decimating LCD DECDRIVER with Level Shifters

获取价格
AD8385ASVZ ADI 10-Bit, 12-Channel Decimating LCD DECDRIVER with Level Shifters

获取价格
AD8386 ADI 10-Bit, 12-Channel Output Decimating LCD Driver

获取价格
AD8386JCPZ ADI 10-Bit, 12-Channel Output Decimating LCD Driver

获取价格

与AD8383ACPZ相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证