AD8382
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
1
2
3
4
5
6
7
8
9
36 VID0
35 AVCC0,1
34 VID1
33 AGND1,2
32 VID2
31 AVCC2,3
30 VID3
PIN 1
INDICATOR
AD8382
TOP VIEW
(Not to Scale)
29 AGND3,4
28 VID4
DB9 10
DB10 11
DB11 12
27 AVCC4,5
26 VID5
25 AGND5
NC = NO CONNECT
Figure 6. 48-Lead LFCSP, 7 mm × 7 mm Package
Table 4. Pin Function Descriptions
Mnemonic
DB(0:11)
CLK
Function
Data Input
Clock
Description
12-Bit Data Input. MSB = DB(11).
Clock Input.
STSQ
Start Sequence
A new data loading sequence begins on the rising edge of CLK when this input was HIGH on
the preceding rising edge of CLK and the E/O input is held HIGH. A new data loading sequence
begins on the falling edge of CLK when this input was HIGH on the preceding falling edge of
CLK and the E/O input is held LOW.
R/L
Right/Left Select
Even/Odd Select
A new data loading sequence begins on the left, with Channel 0, when this input is LOW, and
on the right, with Channel 5, when this input is HIGH.
E/O
The active CLK edge is the rising edge when this input is held HIGH and the falling edge when
this input is held LOW. Data is loaded sequentially on the rising edges of CLK when this input is
HIGH and on the falling edges when this input is LOW.
XFR
Data Transfer
Data is transferred to the outputs on the immediately following falling edge of CLK when this
input is HIGH on the rising edge of CLK.
VID0–VID5
V1,V2
Analog Outputs
These pins are directly connected to the analog inputs of the LCD panel.
Reference Voltages
The voltages applied between these pins and AGND set the reference levels of the analog
outputs.
VREFHI,
VREFLO
Full-Scale References
Invert
The voltage applied between these pins sets the full-scale output voltage.
INV
When this pin is HIGH, the analog output voltages are at or above V2. When this pin is LOW,
the analog output voltages are at or below V1.
DVCC
DGND
AVCCx
AGNDx
BYP
Digital Power Supply
Digital Supply Return
Analog Power Supplies
Analog Supply Returns
Bypass
Digital Power Supply.
This pin is normally connected to the analog ground plane.
Analog Power Supplies.
Analog Supply Returns.
A 0.1 µF capacitor connected between this pin and AGND ensures optimum settling time.
When HIGH, the internal circuits are debiased and the power dissipation drops to a minimum.
STBY
Standby
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