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AD834 PDF预览

AD834

更新时间: 2024-02-09 11:49:12
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
8页 260K
描述
500 MHz Four-Quadrant Multiplier

AD834 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.43
模拟集成电路 - 其他类型:ANALOG MULTIPLIER OR DIVIDER标称带宽:500 MHz
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm湿度敏感等级:1
负电源电压最大值(Vsup):-9 V负电源电压最小值(Vsup):-4 V
标称负供电电压 (Vsup):-5 V最大负输入电压:-1 V
功能数量:1端子数量:8
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
最大正输入电压:1 V电源:+-5 V
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Analog Computational Functions最大供电电流 (Isup):35 mA
最大供电电压 (Vsup):9 V最小供电电压 (Vsup):4 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BIPOLAR温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

AD834 数据手册

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AD834  
POWER MEASUREMENT (MEAN SQUARE AND RMS)  
The AD834 is well suited to measurement of average power in  
high frequency applications, connected either as a multiplier for  
the determination of the V × I product, or as a squarer for use  
with a single input. In these applications, the multiplier is fol-  
lowed by a low-pass filter to extract the long term average value.  
Where the bandwidth extends to several hundred megahertz, the  
first pole of this filter should be formed by grounded capacitors  
placed directly at the output pins W1 and W2. This pole can be  
at a few kilohertz. The effective multiplication or squaring band-  
width is then limited solely by the AD834, since the following  
active circuitry is required to process only low frequency signals.  
path to the second AD834. This increases the maximum input  
capability to +15 dBm and improves the response flatness by  
damping some of the resonances. The overall gain is unity; that  
is, the output voltage is exactly equal to the rms value of the  
input signal. The offset potentiometer at the AD834 outputs ex-  
tends the dynamic range, and is adjusted for a dc output of  
125.7 mV when a 1 MHz sinusoidal input at 5 dBm is applied.  
Additional filtering is provided; the time constants were chosen  
to allow operation down to frequencies as low as 1 kHz and to  
provide a critically damped envelope response, which settles  
typically within 10 ms for a full-scale input (and proportionally  
slower for smaller inputs). The 5 µF and 0.1 µF capacitors may  
be scaled down to reduce response time if accurate rms opera-  
tion at low frequencies is not required. The output op amp must  
be specified to accept a common-mode input near its supply.  
Note that the output polarity may be inverted by replacing the  
NPN transistor with a PNP type.  
(Refer to Figure 5 test configuration.) Using the device as a  
squarer the wideband output in response to a sinusoidal stimu-  
lus is a raised cosine:  
sin2 ωt = (1 cos 2 ωt) /2  
Recall here that the full-scale output current (when full-scale  
input voltages of 1 V are applied to both X and Y) is 4 mA. In a  
50 system, a sinusoid power of +10 dBm has a peak value of  
1 V. Thus, at this drive level the peak output voltage across the  
differential 50 load in the absence of the filter capacitors  
would be 400 mV (that is, 4 mA × 50 Ω × 2), whereas the  
average value of the raised cosine is only 200 mV. The averaging  
configuration is useful in evaluating the bandwidth of the  
AD834, since a dc voltage is easier to measure than a wideband,  
differential output. In fact, the squaring mode is an even more  
critical test than the direct measurement of the bandwidth of  
either channel taken independently (with a dc input on the  
nonsignal channel), because the phase relationship between the  
two channels also affects the average output. For example, a  
time delay difference of only 250 ps between the X and Y chan-  
nels would result in zero output when the input frequency is  
1 GHz, at which frequency the phase angle is 90 degrees and  
the intrinsic product is now between a sine and cosine function,  
which has zero average value.  
Figure 13. Connections for Wideband RMS Measurement  
FREQUENCY DOUBLER  
Figure 14 shows another squaring application. In this case, the  
output filter has been removed and the wideband differential  
output is converted to a single sided signal using a balun,”  
which consists of a length of 50 coax cable fed through a fer-  
rite core (Fair-Rite type 2677006301). No attempt is made to  
reverse terminate the output. Higher load power could be  
achieved by replacing the 50 load resistors by ferrite bead  
inductors. The same precautions should be observed with re-  
gard to PC board layout as recommended above. The output  
spectrum shown in Figure 15 is for an input power of +10 dBm  
at a frequency of 200 MHz. The second harmonic component  
at 400 MHz has an output power of 15 dBm. Some feed-  
through of the fundamental occurs: it is 15 dBs below the main  
output. It is believed that improvements in the design of the  
balun would reduce this feedthrough. A spurious output at  
600 MHz is also present, but it is 30 dBs below the main out-  
put. At an input frequency of 100 MHz, the measured power  
level at 200 MHz is 16 dBm, while the fundamental feed-  
through is reduced to 25 dBs below the main output; at an  
output of 600 MHz the power is 11 dBm and the third  
harmonic at 900 MHz is 32 dBs below the main output.  
The physical construction of the circuitry around the IC is criti-  
cal to realizing the bandwidth potential of the device. The input is  
supplied from an HP8656A signal generator (100 kHz to  
990 MHz) via an SMA connector and terminated by an HP436A  
power meter using an HP8482A sensor head connected via a  
second SMA connector. Since neither the generator nor the  
sensor provide a dc path to ground, a lossy 1 µH inductor L1,  
formed by a 22-gauge wire passing through a ferrite bead (Fair-  
Rite type 2743001112) is included. This provides adequate  
impedance down to about 30 MHz. The IC socket is mounted  
on a ground plane, with a clear area in the rectangle formed by  
the pins. This is important, since significant transformer action  
can arise if the pins pass through individual holes in the board;  
this has been seen to cause an oscillation at 1.3 GHz in improp-  
erly constructed test jigs. The filter capacitors must be  
connected  
directly to the same point on the ground plane via the shortest  
possible leads. Parallel combinations of large and small capaci-  
tors are used to minimize the impedance over the full frequency  
range. (Refer to Figure 1 for mean-square response for the  
AD834 in cerdip package, using the configuration of Figure 5.)  
To provide a square-root response and thus generate the rms  
value at the output, a second AD834, also connected as a  
squarer, can be used, as shown in Figure 13. Note that an at-  
tenuator is inserted both in the signal input and in the feedback  
REV. C  
–7–  

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