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AD8314ARM-REEL PDF预览

AD8314ARM-REEL

更新时间： 2024-01-13 21:25:40
品牌 Logo 应用领域
亚德诺 - ADI 电信集成电路电信电路光电二极管控制器
页数 文件大小 规格书
16页 277K
描述
100 MHz-2500 MHz 45 dB RF Detector/Controller

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AD8314ARM-REEL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.01
JESD-30 代码：S-PDSO-G8JESD-609代码：e3
长度：3 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：SQUARE封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.1 mm标称供电电压：3 V
表面贴装：YES电信集成电路类型：TELECOM CIRCUIT
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3 mmBase Number Matches：1

AD8314ARM-REEL 数据手册

 浏览型号AD8314ARM-REEL的Datasheet PDF文件第10页浏览型号AD8314ARM-REEL的Datasheet PDF文件第11页浏览型号AD8314ARM-REEL的Datasheet PDF文件第12页浏览型号AD8314ARM-REEL的Datasheet PDF文件第14页浏览型号AD8314ARM-REEL的Datasheet PDF文件第15页浏览型号AD8314ARM-REEL的Datasheet PDF文件第16页 
AD8314  
3.5V  
The setpoint voltage, in the range 0 V to 1.1 V, is applied to the  
VSET pin of the AD8314. This will typically be supplied by a  
Digital-to-Analog Converter (DAC). This voltage is compared  
to the input level to the AD8314. Any imbalance is between VSET  
and the RF input level is corrected by V_DN, which drives the  
VAPC (gain control) of the power amplifier. V_DN reaches a  
maximum value of approximately 1.9 V on a 2.7 V supply (this  
will be higher for higher supply voltages) while delivering approxi-  
mately 3 mA to the VAPC input.  
47␮F  
2.2␮F  
680pF  
TO  
ANTENNA  
+35dBm  
MAX  
DC09-73  
RF INPUT  
A filter capacitor (CF) must be used to stabilize the loop. The  
choice of CF will depend to a large degree on the gain control  
dynamics of the power amplifier, something that is frequently  
poorly characterized, so some trial and error may be necessary.  
In this example, a 220 pF capacitor gives the loop sufficient  
speed to follow the GSM and DCS1800 time slot ramping profiles,  
while still having a stable, critically-damped response.  
6
4
P
IN  
0dBm  
BGY241  
3
5
+15dBm  
1
2
ATTN  
15dB  
52.3⍀  
0.1␮F  
0dBm  
MAX  
V
S
RFIN  
ENBL  
VSET  
FLTR  
VPOS  
Figure 35 shows the relationship between the setpoint voltage,  
2.7V  
V
SET and output power, at 0.9 GHz. The overall gain control  
V
S
V DN  
V UP  
function is linear in dB for a dynamic range of over 40 dB.  
AD8314  
V
SET  
Figure 36 shows a similar circuit for a single band handset power  
amplifier. The BGY241 (Phillips) is driven by a nominal power  
level of 0 dBm. A 20 dB directional coupler, DC09-73 (Alpha) is  
used to couple the signal in this case. Figure 37 shows the rela-  
tionship between the control voltage and the output power at  
0.9 GHz.  
0V–1.1V  
COMM  
C
F
220pF  
In both of these examples, noise on the V_DN pin can be reduced  
by placing a simple RC low-pass filter between VDN and the gain  
control pin of the power amplifier. However, the value of the  
resistor should be kept low to minimize the voltage drop across  
it due to the dc current flowing into the gain control input.  
Figure 36. A Single Mode Power Amplifier Control Circuit  
40  
30  
20  
10  
40  
30  
20  
10  
0
0
–10  
–20  
–30  
–40  
–50  
–10  
0
0.2  
0.4  
0.6  
0.8  
1.0  
VSET – Volts  
–20  
–30  
Figure 37. POUT vs. VSET at 0.9 GHz for Single Mode  
Handset  
0
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
VSET – Volts  
Figure 35. POUT vs. VSET at 0.9 GHz for Dual Mode  
Handset Power Amplifier Application  
REV. 0  
–13–  
1...10111213141516

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