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AD8170

更新时间： 2024-02-21 08:40:56
品牌 Logo 应用领域
亚德诺 - ADI 复用器开关放大器
页数 文件大小 规格书
16页 476K
描述
250 MHz, 10 ns Switching Multiplexers w/Amplifier

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AD8170 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：0.95
模拟集成电路 - 其他类型：VIDEO MULTIPLEXERJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
湿度敏感等级：1标称负供电电压 (Vsup)：-5 V
信道数量：2功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：+-5 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Multiplexer or Switches最大供电电流 (Isup)：11 mA
标称供电电压 (Vsup)：5 V表面贴装：YES
最长接通时间：17 ns技术：BIPOLAR
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：3.9 mmBase Number Matches：1

AD8170 数据手册

 浏览型号AD8170的Datasheet PDF文件第5页浏览型号AD8170的Datasheet PDF文件第6页浏览型号AD8170的Datasheet PDF文件第7页浏览型号AD8170的Datasheet PDF文件第9页浏览型号AD8170的Datasheet PDF文件第10页浏览型号AD8170的Datasheet PDF文件第11页 
AD8170/AD8174  
THEORY OF OPERATION  
General  
Bringing SD high shuts off the supply current for all the switches,  
that some of the logic control circuitry and the amplifier,  
reducing the quiescent current drain to 1.5 mA. If the  
ENABLE and SD functions are not to be used, those respective  
pins must be tied to ground for proper operation. Any unused  
channel input should also be tied to ground.  
The AD8170/AD8174 multiplexers integrate wideband analog  
switches with a high speed current feedback amplifier. The  
input switches are complementary bipolar follower stages that  
are turned on and off by using a current steering technique that  
attains switch times of less than 10 ns and ensures low switching  
transients. The 250 MHz current feedback amplifier provides  
up to 50 mA of drive current. Overall gain and frequency  
response are set by external resistors for maximum versatility.  
The AD8170 has two switches driving an amplifier to form a 2:1  
multiplexer. No disable or shutdown functions are provided.  
DC Performance and Noise Considerations  
Figure 23 shows the different contributors to total output offset  
and noise. Total expected output offset can be calculated using  
Equation 1 below:  
Figure 22 is a block diagram of the multiplexer signal chain,  
with a simplified schematic of an input switch. When the  
channel is on (i.e., VONB more positive than VREFB, VONT more  
negative than VREFT), I2 flows through Q1 and Q2, and I3 flows  
through Q3 and Q4. This biases up Q5 through Q8 to form the  
unity gain follower. I1 and I4 (the “off” currents) are steered,  
either to another switch or to the power supply. When the  
channel turns off, I2 and I3 are steered away while I1 switches  
over to pull the base of Q8 up to VCLT + 1 VBE (about 2.7 volts  
from ground reference) and I4 switches over to pull the base of  
Q5 down to VCLB – 1 VBE (about –2.7 volts away from ground  
reference). Clamping the bases of the reverse biased output  
transistors to a low impedance point greatly improves isolation  
performance.  
RF  
RG  
−
VOS out =  
I
+ × RS +V  
1+  
+ I × RF  
(
)
(
[
)
(
)
B
OS  
B
]
(1)  
SWITCH  
R
BUFFER  
S
V
IN  
+
+
I
/I  
en  
B
R
F
V
/V  
OS en  
V
OUT  
R
–
–
G
I
/I  
en  
B
The AD8174 has four switches with outputs wired together and  
driving the positive input of a current feedback amplifier to form  
a 4:1 multiplexer. It is designed so that only one channel is on  
at a time. By bringing ENABLE high, the supply current for the  
amplifier is shut off. This turns the output of the amplifier into  
a high impedance, allowing the AD8174 to be used in larger  
arrays. In practice, the disabled output impedance of the mux  
will be determined by the amplifier’s feedback network.  
Figure 23. DC Errors for Buffered Multiplexer  
Equations 2 and 3 below can be used to predict the output  
voltage noise of the multiplexer for different choices of gains  
and external resistors. The different contributions to output  
noise are root-sum-squared to calculate total output noise  
spectral density in Equation 2. As there is no peaking in the  
multiplier’s noise characteristic, the total peak-to-peak output  
noise will be accurately predicted using Equation 3.  
2
2
2
2
V EN  
nV / Hz  
=
I
EN  
+ × RS 2 + V EN  
1+  
+ IEN– × RF 2 +4KT RF + RS 1+  
+ RG  
RF  
RG  
RF  
RG  
RF  
RG  
(OUT )  
(
)
(
)
(
)
(
)
(2)  
(3)  
VEN p−p =VEN  
×
f
−3dB ×6.2×1. 26  
IN0  
IN1  
IN2  
VOUT  
VFB  
I1  
I3  
I6  
VREFT  
VOFFT  
IN3  
VONT  
VREFT  
Q5  
Q6  
Q3  
Q4  
Q1  
VCLB  
Q7  
Q8  
Q2  
VCLT  
VOFFB  
VONB  
VREFB  
VREFB  
I4  
I2  
Figure 22. Block Diagram and Simplified Schematic of the AD8170  
–8–  
REV. 0  
1...567891011...16

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