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AD8133ACPZ-REEL7

更新时间： 2024-02-23 05:00:49
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 驱动接口集成电路驱动器
页数 文件大小 规格书
17页 1551K
描述
TRIPLE LINE DRIVER, QCC24, 4 X 4 MM, LEAD FREE, MO-220VGGD-2, LFCSP-24

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AD8133ACPZ-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：0.89
差分输出：YES驱动器位数：3
输入特性：DIFFERENTIAL接口集成电路类型：LINE DRIVER
接口标准：GENERAL PURPOSEJESD-30 代码：S-XQCC-N24
JESD-609代码：e3长度：4 mm
湿度敏感等级：3标称负供电电压：-5 V
功能数量：3端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
最大接收延迟：座面最大高度：1 mm
最大供电电压：6 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：BIPOLAR温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：4 mm
Base Number Matches：1

AD8133ACPZ-REEL7 数据手册

 浏览型号AD8133ACPZ-REEL7的Datasheet PDF文件第10页浏览型号AD8133ACPZ-REEL7的Datasheet PDF文件第11页浏览型号AD8133ACPZ-REEL7的Datasheet PDF文件第12页浏览型号AD8133ACPZ-REEL7的Datasheet PDF文件第14页浏览型号AD8133ACPZ-REEL7的Datasheet PDF文件第15页浏览型号AD8133ACPZ-REEL7的Datasheet PDF文件第16页 
AD8133  
THEORY OF OPERATION  
Each differential driver in the AD8133 differs from a conven-  
tional op amp in that it has two outputs whose voltages move in  
opposite directions. Like an op amp, it relies on high open-loop  
gain and negative feedback to force these outputs to the desired  
voltages. The AD8133 drivers make it easy to perform single-  
ended-to-differential conversion, common-mode level shifting,  
and amplification of differential signals.  
Common-mode voltage refers to the average of two node volt-  
ages with respect to a common reference. The output common-  
mode voltage is defined as  
(VOP +VON  
)
VOUT,cm  
=
2
Output Balance  
Output balance is a measure of how well the differential output  
signals are matched in amplitude and how close they are to  
exactly 180° apart in phase. Balance is most easily determined  
by placing a well-matched resistor divider between the differen-  
tial output voltage nodes and comparing the magnitude of the  
signal at the divider’s midpoint with the magnitude of the dif-  
ferential signal. By this definition, output balance error is the  
magnitude of the change in output common-mode voltage  
divided by the magnitude of the change in output differential-  
mode voltage in response to a differential input signal.  
Previous differential drivers, both discrete and integrated  
designs, have been based on using two independent amplifiers  
and two independent feedback loops, one to control each of the  
outputs. When these circuits are driven from a single-ended  
source, the resulting outputs are typically not well balanced.  
Achieving a balanced output has typically required exceptional  
matching of the amplifiers and feedback networks.  
DC common-mode level shifting has also been difficult with  
previous differential drivers. Level shifting has required the use  
of a third amplifier and feedback loop to control the output  
common-mode level. Sometimes, the third amplifier has also  
been used to attempt to correct an inherently unbalanced  
circuit. Excellent performance over a wide frequency range has  
proven difficult with this approach.  
∆VOUT,cm  
Output Balance Error =  
∆VOUT,dm  
ANALYZING AN APPLICATION CIRCUIT  
The AD8133 uses high open-loop gain and negative feedback to  
force its differential and common-mode output voltages to  
minimize the differential and common-mode input error  
voltages. The differential input error voltage is defined as the  
voltage between the differential inputs labeled VAP and VAN in  
Figure 34. For most purposes, this voltage can be assumed to be  
zero. Similarly, the difference between the actual output  
common-mode voltage and the voltage applied to VOCM can also  
be assumed to be zero. Starting from these two assumptions, any  
application circuit can be analyzed.  
Each of the AD8133 drivers uses two feedback loops to  
separately control the differential and common-mode output  
voltages. The differential feedback, set by the internal resistors,  
controls only the differential output voltage. The internal  
common-mode feedback loop controls only the common-mode  
output voltage. This architecture makes it easy to arbitrarily set  
the output common-mode level by simply applying a voltage to  
the VOCM input. The output common-mode voltage is forced, by  
internal common-mode feedback, to equal the voltage applied to  
the VOCM input, without affecting the differential output voltage.  
CLOSED-LOOP GAIN  
The AD8133 architecture results in outputs that are highly  
balanced over a wide frequency range without requiring exter-  
nal components or adjustments. The common-mode feedback  
loop forces the signal component of the output common-mode  
voltage to be zeroed. The result is nearly perfectly balanced dif-  
ferential outputs of identical amplitude that are exactly 180°  
apart in phase.  
The differential mode gain of the circuit in Figure 34 can be  
described by the following equation.  
VOUT,dm  
VIN,dm  
RF  
RG  
=
= 2  
where RF = 1.5 kΩ and RG = 750 Ω nominally.  
DEFINITION OF TERMS  
R
F
Differential Voltage  
V
R
AP  
AN  
G
G
+
V
V
ON  
Differential voltage refers to the difference between two node  
voltages that are balanced with respect to each other. For exam-  
ple, in Figure 34 the output differential voltage (or equivalently  
output differential mode voltage) is defined as  
IP  
OCM  
V
R
V
V
L, dm  
OUT, dm  
IN, dm  
–
V
V
OP  
IN  
V
R
R
F
Figure 34.  
VOUT,dm  
=
(
VOP −VON  
)
Rev. 0 | Page 12 of 16  
 
 
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