Fiber Optic Receiver with Quantizer and
Clock Recovery and Data Retiming
a
AD807
FEATURES
Meets CCITT G.958 Requirem ents
for STM-1 Regenerator—Type A
frequency acquisition without false lock. T his eliminates a reli-
ance on external components such as a crystal or a SAW filter,
to aid frequency acquisition.
Meets Bellcore TR-NWT-000253 Requirem ents for OC-3
Output J itter: 2.0 Degrees RMS
155 Mbps Clock Recovery and Data Retim ing
Accepts NRZ Data, No Pream ble Required
Phase-Locked Loop Type Clock Recovery—
No Crystal Required
T he AD807 acquires frequency and phase lock on input data
using two control loops that work without requiring external
control. T he frequency acquisition control loop initially acquires
the frequency of the input data, acquiring frequency lock on
random or scrambled data without the need for a preamble. At
frequency lock, the frequency error is zero and the frequency
detector has no further effect. T he phase acquisition control
loop then works to ensure that the output phase tracks the input
phase. A patented phase detector has virtually eliminated pat-
tern jitter throughout the AD807.
Quantizer Sensitivity: 2 m V
Level Detect Range: 2.0 m V to 30 m V
Single Supply Operation: +5 V or –5.2 V
Low Pow er: 170 m W
10 KH ECL/ PECL Com patible Output
Package: 16-Pin Narrow 150 m il SOIC
T he device VCO uses a ring oscillator architecture and patented
low noise design techniques. Jitter is 2.0 degrees rms. T his low
jitter results from using a fully differential signal architecture,
Power Supply Rejection Ratio circuitry and a dielectrically
isolated process that provides immunity from extraneous signals
on the IC. T he device can withstand hundreds of millivolts of
power supply noise without an effect on jitter performance.
P RO D UCT D ESCRIP TIO N
T he AD807 provides the receiver functions of data quantiza-
tion, signal level detect, clock recovery and data retiming for
155 Mbps NRZ data. T he device, together with a PIN
diode/preamplifier combination, can be used for a highly inte-
grated, low cost, low power SONET OC-3 or SDH ST M-1
fiber optic receiver.
T he user sets the jitter peaking and acquisition time of the PLL
by choosing a damping factor capacitor whose value determines
loop damping. CCIT T G.958 T ype A jitter transfer require-
ments can easily be met with a damping factor of 5 or greater.
T he receiver front end signal level detect circuit indicates when
the input signal level has fallen below a user adjustable thresh-
old. T he threshold is set with a single external resistor. T he sig-
nal level detect circuit 3 dB optical hysteresis prevents chatter at
the signal level detect output.
Device design guarantees that the clock output frequency will
drift by less than 20% in the absence of input data transitions.
Shorting the damping factor capacitor, CD, brings the clock out-
put frequency to the VCO center frequency.
T he AD807 consumes 140 mW and operates from a single
power supply at either +5 V or –5.2 V.
T he PLL has a factory trimmed VCO center frequency and a
frequency acquisition control loop that combine to guarantee
FUNCTIO NAL BLO CK D IAGRAM
CF1 CF2
QUANTIZER
PIN
COMPENSATING
ZERO
LOOP
FILTER
Φ
∑
DET
NIN
PHASE-LOCKED LOOP
VCO
SIGNAL
THRADJ
LEVEL
F
CLKOUTP
CLKOUTN
DET
DETECTOR
LEVEL
DATAOUTP
DATAOUTN
RETIMING
DEVICE
DETECT
COMPARATOR/
BUFFER
AD807
SDOUT
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
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