Datasheet > 信号电路 > 锁相环或频率合成电路> AD802-155KR

AD802-155KR

更新时间： 2024-02-17 06:17:43

品牌	Logo	应用领域
亚德诺 - ADI		信号电路锁相环或频率合成电路光电二极管时钟
页数	文件大小	规格书
12页	255K
描述
Clock Recovery and Data Retiming Phase-Locked Loop

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中文翻译

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技术参数
数据手册

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AD802-155KR 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	20
Reach Compliance Code：	unknown	风险等级：	5.43
Is Samacsys：	N	其他特性：	ALSO OPERATES ON -5.2 VOLT SUPPLY
模拟集成电路 - 其他类型：	PHASE LOCKED LOOP	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	长度：	12.8 mm
湿度敏感等级：	NOT SPECIFIED	功能数量：	1
端子数量：	20	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	220
认证状态：	COMMERCIAL	座面最大高度：	2.64 mm
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	7.5 mm	Base Number Matches：	1

AD802-155KR 数据手册

AD800/AD802

TH EO RY O F O P ERATIO N

T he damping ratio of the phase-locked loop is user program-

mable with a single external capacitor. At 155 MHz a damping

ratio of 10 is obtained with a 0.22 µF capacitor. More generally,

T he AD800 and AD802 are phase-locked loop circuits for re-

covery of clock from NRZ data. T he architecture uses a fre-

quency detector to aid initial frequency acquisition, refer to

Figure 21 for a block diagram. Note the frequency detector is al-

ways in the circuit. When the PLL is locked, the frequency error

is zero and the frequency detector has no further effect. Since

the frequency detector is always in circuit, no control functions

are needed to initiate acquisition or change mode after acquisi-

tion. T he frequency detector also supplies a frequency acquisi-

tion (FRAC) output to indicate when the loop is acquiring lock.

During the frequency acquisition process the FRAC output is a

series of pulses of width equal to the period of the VCO. T hese

pulses occur on the cycle slips between the data frequency and

the VCO frequency. With a maximum density (1010 . . .) data

pattern, every cycle slip will produce a pulse at FRAC. How-

ever, with random data, not every cycle slip produces a pulse.

T he density of pulses at FRAC increases with the density of

data transitions. T he probability that a cycle slip will produce a

pulse increases as the frequency error approaches zero. After the

frequency error has been reduced to zero, the FRAC output will

have no further pulses. At this point the PLL begins the process

of phase acquisition, with a settling time of roughly 2000 bit pe-

riods. Valid retimed data can be guaranteed by waiting 2000 bit

periods after the last FRAC pulse has occurred.

1. 7 × f _DATA× C_D

the damping ratio scales as

. At 155 MHz a

damping ratio of 1 is obtained with a 2.2 nF capacitor. A lower

damping ratio allows a faster frequency acquisition; generally

the acquisition time scales directly with the capacitor value.

However, at damping ratios approaching one, the acquisition

time no longer scales directly with the capacitor value. T he

acquisition time has two components: frequency acquisition and

phase acquisition. T he frequency acquisition always scales with

capacitance, but the phase acquisition is set by the loop

bandwidth of the PLL and is independent of the damping ratio.

T hus, the 0.08% fractional loop bandwidth sets a minimum

acquisition time of 15,000 bit periods. Note the acquisition time

for a damping factor of 1 is specified as 15,000 bit periods. T his

comprises 13,000 bit periods for frequency acquisition and

2,000 periods for phase acquisition. Compare this to the

400,000 bit periods acquisition time specified for a damping

ratio of 5; this consists entirely of frequency acquisition, and the

2,000 bit periods of phase acquisition is negligible.

While lower damping ratio affords faster acquisition, it also

allows more peaking in the jitter transfer response (jitter

peaking). For example, with a damping ratio of 10 the jitter

peaking is 0.02 dB, but with a damping factor of 1, the peaking

is 2 dB.

Jitter caused by variations of density of data transitions (pattern

jitter) is virtually eliminated by use of a new phase detector

(patented). Briefly, the measurement of zero phase error does

not cause the VCO phase to increase to above the average run

rate set by the data frequency. T he jitter created by a 2⁷–1

pseudo-random code is 1/2 degree, and this is small compared

to random jitter.

DATA

INPUT

TS + 1

∑

DET

VCO

RECOVERED

DET

T he jitter bandwidth for the AD802-155 is 0.08% of the center

frequency. T his figure is chosen so that sinusoidal input jitter at

130 kHz will be attenuated by 3 dB. T he jitter bandwidths of

the AD800-45 and AD800-52 are 0.1% of the respective center

frequencies. T he jitter bandwidth of the AD800 or the AD802 is

mask programmable from 0.01% to 1% of the center frequency.

A device with a very low loop bandwidth (0.01% of the center

frequency) could effectively filter (clean up) a jittery timing

reference. Consult the factory if your application requires a

special loop bandwidth.

CLOCK OUTPUT

RETIMED

DATA OUTPUT

RETIMING

DEVICE

FRAC OUTPUT

Figure 21. AD800 and AD802 Block Diagram

–8–

REV. B

1...5 6 789 10 11 12

中文翻译

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与AD802-155KR相关器件

型号	品牌	获取价格	描述	数据表
AD802-155KR-REEL	ADI	获取价格	暂无描述
AD8021AR	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARM	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARM-REEL	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARM-REEL7	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARMZ	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARMZ-REEL	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021ARMZ-REEL7	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021AR-REEL	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems
AD8021AR-REEL7	ADI	获取价格	Low Noise, High Speed Amplifier for 16-Bit Systems

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