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AD8012AR PDF预览

AD8012AR

更新时间: 2024-02-06 21:20:01
品牌 Logo 应用领域
亚德诺 - ADI 放大器
页数 文件大小 规格书
15页 417K
描述
Dual 350 MHz Low Power Amplifier

AD8012AR 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:1.65
Is Samacsys:N放大器类型:OPERATIONAL AMPLIFIER
最大平均偏置电流 (IIB):15 µA标称共模抑制比:60 dB
最大输入失调电压:4000 µVJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
湿度敏感等级:1负供电电压上限:-6.3 V
标称负供电电压 (Vsup):-5 V功能数量:2
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.75 mm
标称压摆率:2250 V/us子类别:Operational Amplifier
供电电压上限:6.3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BIPOLAR
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

AD8012AR 数据手册

 浏览型号AD8012AR的Datasheet PDF文件第9页浏览型号AD8012AR的Datasheet PDF文件第10页浏览型号AD8012AR的Datasheet PDF文件第11页浏览型号AD8012AR的Datasheet PDF文件第13页浏览型号AD8012AR的Datasheet PDF文件第14页浏览型号AD8012AR的Datasheet PDF文件第15页 
AD8012  
TO  
RECEIVER  
CIRCUITRY  
APPLICATIONS  
Line Driving for HDSL  
+5V  
High Bitrate Digital Subscriber Line (HDSL) is becoming  
popular as a means of providing full duplex data communication  
at rates up to 1.544 MBPS or 2.048 MBPS over moderate dis-  
tances via conventional telephone twisted pair wires. Traditional  
T1 (E1 in Europe) requires repeaters every 3,000 feet to 6,000  
feet to boost the signal strength and allow transmission over  
distances of up to 12,000 feet. In order to achieve repeaterless  
transmission over this distance, an HDSL modem requires  
transmitted power level of +13.5 dBm (assuming a line imped-  
ance of 135 ).  
0.1F  
1/2  
UP TO  
12,000 FEET  
AD8012  
+
66.5⍀  
R
F
750⍀  
R
G
1.5k⍀  
R
F
750⍀  
12V p-p  
6V p-p  
135⍀  
6V p-p  
66.5⍀  
1:1  
1:1  
0.1F  
1/2  
AD8012  
HDSL uses the Two Binary/One Quaternary line code (2B1Q).  
A sample 2B1Q waveform is shown in Figure 41. The digital bit  
stream is broken up into groups of two bits. Four analogue  
voltages (called quaternary symbols) are used to represent the  
four possible combinations of two bits. These symbols are as-  
signed arbitrary names +3, +1, –1 and –3. The corresponding  
voltage levels are produced by a DAC that is usually part of an  
Analog Front End Circuit (AFEC). Before being applied to the  
line, the DAC output is low-pass filtered and acquires the sinu-  
soidal form shown in Figure 41. Finally, the filtered signal is  
applied to the line driver. The line voltages that correspond to  
the quaternary symbols +3, +1, –1 and –3 are 2.64 V, 0.88 V,  
–0.88 V and –2.64 V. This gives a peak-to-peak line voltage of  
5.28 V.  
–5V  
GAIN = +2  
TO  
RECEIVER  
CIRCUITRY  
Figure 42. Differential for HDSL Applications  
The immediate effect of back-termination is that the signal from  
the amplifier is halved before being applied to the line. This  
doubles the power the amplifier must deliver. However, the  
back-termination resistors also play an important second role.  
Full-duplex data transmission systems like HDSL simulta-  
neously transmit data in both directions. As a result, the signal  
on the line and across the back termination resistors is the com-  
posite of the transmitted and received signal. The termination  
resistors are used to tap off this signal and feed it to the receive  
circuitry. Because the receive circuitry “knows” what is being  
transmitted, the transmitted data can be subtracted from the  
digitized composite signal to reveal the received data.  
SYMBOL  
DAC  
VOLTAGE  
2.64V  
NAME  
+3  
OUTPUT  
FILTERED  
OUTPUT  
TO LINE  
DRIVER  
Driving a line with a differential signal offers a number of ad-  
vantages compared to a single-ended drive. Because the two  
outputs are always 180 degrees out of phase relative to one  
another, the differential signal output is double the output am-  
plitude of either of the op amps. As a result, the differential  
amplifier can have a peak-to-peak swing of 16 V (each op amp  
can swing to ±4 V), even though the power supply is ±5 V.  
+1  
0.88V  
–1  
–3  
–0.88V  
–2.64V  
In addition to this, even-order harmonics (2nd, 4th, 6th, etc.) of  
the two single-ended outputs tend to cancel out one another, so  
the Total Harmonic Distortion (quadratic sum of all harmonics)  
decreases compared to the single-ended case, even as the signal  
amplitude is doubled. This is particularly advantageous for the  
case of the second harmonic. As it is very close to the funda-  
mental, filtering becomes difficult. In this application, the THD  
is dominated by the third harmonic which is 65 dB below the  
carrier (i.e., Spurious Free Dynamic Range = –65 dBc).  
–1 +3  
01 10  
+1  
11  
–3  
00  
–3 +1 +3  
00 11 10  
–3  
00  
–1  
01  
–1 +1  
01 11  
–1  
01  
–3  
00  
Figure 41. Time Domain Representation of a HDSL Signal  
Many of the elements of a classic differential line driver are  
shown in the HDSL line driver in Figure 42. A 6 V peak-to-  
peak differential signal is applied to the input. The differential  
gain of the amplifier (1+2 RF/RG) is set to +2, so the resulting  
differential output signal is 12 V p-p.  
As is normal in telephony applications, a transformer galvani-  
cally isolates the differential amplifier from the line. In this case  
a 1:1 turns ratio is used. In order to correctly terminate the line,  
it is necessary to set the output impedance of the amplifier to be  
equal to the impedance of the line being driven (135 in this  
case). Because the transformer has a turns ratio of 1:1, the im-  
pedance reflected from the line is equal to the line impedance  
of 135 (RREFL = RLINE/Turns Ratio2). As a result, two 66.5 Ω  
resistors correctly terminate the line.  
Differential line driving also helps to preserve the integrity of  
the transmitted signal in the presence of Electro-Magnetic In-  
terference (EMI). EMI tends to induce itself equally on to both  
the positive and negative signal line. As a result, a receiver with  
good common-mode rejection, will amplify the original signal  
while rejecting induced (common-mode) EMI.  
–12–  
REV. A  

AD8012AR 替代型号

型号 品牌 替代类型 描述 数据表
AD8012ARZ ADI

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