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AD80066KRSZ

更新时间： 2024-01-12 23:39:17
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器光电二极管PC
页数 文件大小 规格书
20页 333K
描述
Complete 16-Bit CCD/CIS Signal Processor

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AD80066KRSZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP,针数：28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：7.92
Is Samacsys：N桶式移位器：NO
边界扫描：NO外部数据总线宽度：8
格式：FIXED POINTJESD-30 代码：R-PDSO-G28
JESD-609代码：e3长度：10.2 mm
低功率模式：YES湿度敏感等级：1
端子数量：28最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：2 mm
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：5.3 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

AD80066KRSZ 数据手册

 浏览型号AD80066KRSZ的Datasheet PDF文件第14页浏览型号AD80066KRSZ的Datasheet PDF文件第15页浏览型号AD80066KRSZ的Datasheet PDF文件第16页浏览型号AD80066KRSZ的Datasheet PDF文件第18页浏览型号AD80066KRSZ的Datasheet PDF文件第19页浏览型号AD80066KRSZ的Datasheet PDF文件第20页 
AD80066  
CIRCUIT OPERATION  
ANALOG INPUTS—CDS MODE  
EXTERNAL INPUT COUPLING CAPACITORS  
Figure 17 shows the analog input configuration for the CDS  
mode of operation. Figure 18 shows the internal timing for the  
sampling switches. The CCD reference level is sampled when  
CDSCLK1 transitions from high to low, opening S1. The CCD  
data level is sampled when CDSCLK2 transitions from high to  
low, opening S2. S3 is then closed, generating a differential  
output voltage that represents the difference between the two  
sampled levels.  
The recommended value for the input coupling capacitors is  
0.1 μF. Although it is possible to use a smaller capacitor, this  
larger value is preferable for several reasons:  
•
•
•
Signal attenuation: The input coupling capacitor creates  
a capacitive divider using the input capacitance from an  
integrated CMOS circuit, which, in turn, attenuates the  
CCD signal level. CIN should be large relative to the 10 pF  
input capacitance of the IC in order to minimize this effect.  
Linearity: Some of the input capacitance of a CMOS IC is  
junction capacitance, which varies nonlinearly with applied  
voltage. If the input coupling capacitor is too small, the  
attenuation of the CCD signal varies nonlinearly with signal  
level. This degrades the system linearity performance.  
Sampling errors: The internal 2 pF sampling capacitors retain  
a memory of the previously sampled pixel. There is a charge  
redistribution error between CIN and the internal sample  
capacitors for larger pixel-to-pixel voltage swings. As the  
value of CIN is reduced, the resulting error in the sampled  
voltage increases. With a CIN value of 0.1 μF, the charge  
redistribution error is less than 1 LSB for a full-scale, pixel-  
to-pixel voltage swing.  
The input clamp is controlled by CDSCLK1. When CDSCLK1  
is high, S4 closes and the internal bias voltage is connected to  
the analog input. The bias voltage charges the external 0.1 μF  
input capacitor, level-shifting the CCD signal into the input  
common-mode range of the AD80066. The time constant of the  
input clamp is determined by the internal 5 kΩ resistance and  
the external 0.1 μF input capacitance.  
AD80066  
S1  
2pF  
VINA  
CCD SIGNAL  
CML  
CML  
C
IN  
0.1µF  
S3  
5kΩ  
S2  
2pF  
AVDD  
S4  
1.7kΩ  
2.2kΩ  
6.9kΩ  
OFFSET  
0.1µF  
+
1µF  
3V  
Figure 17. CDS Mode Input Configuration (All Four Channels Are Identical)  
S1, S4 CLOSED  
S1, S4 CLOSED  
CDSCLK1  
CDSCLK2  
S1, S4 OPEN  
S2 CLOSED  
S2 CLOSED  
S2 OPEN  
S3 OPEN  
S3 CLOSED  
S3 CLOSED  
Q3  
(INTERNAL)  
Figure 18. CDS Mode Internal Switch Timing  
Rev. A | Page 17 of 20  
 
 
 
 
 
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