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AD7873ARQZ-REEL7 PDF预览

AD7873ARQZ-REEL7

更新时间: 2024-01-19 07:46:58
品牌 Logo 应用领域
亚德诺 - ADI 商用集成电路光电二极管
页数 文件大小 规格书
29页 600K
描述
Touch Screen Digitizer

AD7873ARQZ-REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5
其他特性:FUNCTIONALLY IT OPERATES FROM 2.2 TO 5.25V商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:4.9022 mm湿度敏感等级:1
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.7526 mm最大压摆率:0.38 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.2 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9116 mm
Base Number Matches:1

AD7873ARQZ-REEL7 数据手册

 浏览型号AD7873ARQZ-REEL7的Datasheet PDF文件第20页浏览型号AD7873ARQZ-REEL7的Datasheet PDF文件第21页浏览型号AD7873ARQZ-REEL7的Datasheet PDF文件第22页浏览型号AD7873ARQZ-REEL7的Datasheet PDF文件第24页浏览型号AD7873ARQZ-REEL7的Datasheet PDF文件第25页浏览型号AD7873ARQZ-REEL7的Datasheet PDF文件第26页 
AD7873  
Data Sheet  
16 Clocks per Cycle  
using 12 DCLKs to perform the conversion and 3 DCLKs to  
acquire the analog input. This effectively increases the  
throughput rate of the AD7873 beyond that used for the  
specifications that are tested using 16 DCLKs per cycle, and  
DCLK = 2 MHz.  
The control bits for the next conversion can be overlapped with  
the current conversion to allow for a conversion every 16 DCLK  
cycles, as shown in Figure 38. This timing diagram also allows  
the possibility of communication with other serial peripherals  
between each byte (eight DCLKs) transfer between the  
8-Bit Conversion  
processor and the converter. However, the conversion must  
complete within a short enough time frame to avoid capacitive  
droop effects that could distort the conversion result. It should  
also be noted that the AD7873 is fully powered while other  
serial communications are taking place between byte transfers.  
The AD7873 can be set up to operate in an 8-bit mode rather  
than a 12-bit mode by setting the MODE bit in the control  
register to 1. This mode allows a faster throughput rate to be  
achieved, assuming 8-bit resolution is sufficient. When using 8-bit  
mode, a conversion is complete four clock cycles earlier than in  
12-bit mode. This can be used with serial interfaces that provide  
12 clock transfers, or two conversions can be completed with  
three 8-clock transfers. The throughput rate increases by 25% as  
a result of the shorter conversion cycle, but the conversion itself  
can occur at a faster clock rate because the internal settling time  
of the AD7873 is not as critical, because settling to eight bits is  
all that is required. The clock rate can be as much as 50% faster.  
The faster clock rate and fewer clock cycles combine to provide  
double the conversion rate.  
15 Clocks per Cycle  
Figure 39 shows the fastest way to clock the AD7873. This  
scheme does not work with most microcontrollers or DSPs  
because they are not capable of generating a 15 clock cycle per  
serial transfer. However, some DSPs allow the number of clocks  
per cycle to be programmed. This method can also be used with  
FPGAs (field programmable gate arrays) or ASICs (application  
specific integrated circuits). As in the 16 clocks per cycle case,  
the control bits for the next conversion are overlapped with the  
current conversion to allow a conversion every 15 DCLK cycles  
CS  
1
8
1
8
1
8
1
DCLK  
DIN  
S
S
CONTROL BITS  
CONTROL BITS  
BUSY  
DOUT  
11  
10  
9
8
7
6
5
4
3
2
1
0
11  
10  
9
Figure 38. Conversion Timing, 16 DCLKs per Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.  
CS  
1
15  
1
15  
1
DCLK  
SER/  
DFR  
SER/  
MODE  
A2 A1 A0  
DFR  
S
A2 A1 A0 MODE  
PD1 PD0  
DIN  
S
5
PD1 PD0  
S
A2  
BUSY  
DOUT  
11  
10  
9
8
7
6
4
3
2
1
0
11 10  
9
8
7
6
5
4
Figure 39. Conversion Timing, 15 DCLKs per Cycle, Maximum Throughput Rate  
Rev. F | Page 22 of 28  
 
 

AD7873ARQZ-REEL7 替代型号

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