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AD7741YR-REEL7 PDF预览

AD7741YR-REEL7

更新时间： 2024-01-05 04:20:05
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管转换器
页数 文件大小 规格书
12页 148K
描述
VOLTAGE-FREQUENCY CONVERTER, 6.144MHz, PDSO8, 0.150 INCH, SOIC-8

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中文翻译

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AD7741YR-REEL7 技术参数

Source Url Status Check Date：2013-05-01 14:56:20.251是否无铅： 含铅
是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP8,.25
针数：8Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.34转换器类型：VOLTAGE TO FREQUENCY CONVERTER
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：4.9 mm最大线性误差 (EL)：0.024%
湿度敏感等级：1功能数量：1
端子数量：8最大工作频率：6.144 MHz
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：240
最大正输入电压：2.5 V电源：5 V
认证状态：Not Qualified座面最大高度：2.59 mm
子类别：Analog Special Function Converters最大压摆率：8 mA
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3.9 mm
Base Number Matches：1

AD7741YR-REEL7 数据手册

 浏览型号AD7741YR-REEL7的Datasheet PDF文件第6页浏览型号AD7741YR-REEL7的Datasheet PDF文件第7页浏览型号AD7741YR-REEL7的Datasheet PDF文件第8页浏览型号AD7741YR-REEL7的Datasheet PDF文件第9页浏览型号AD7741YR-REEL7的Datasheet PDF文件第11页浏览型号AD7741YR-REEL7的Datasheet PDF文件第12页 
AD7741/AD7742  
APPLICATIONS  
f
OUT  
The basic connection diagram for the part is shown in Figure 9.  
In the connection diagram shown, the AD7742 analog inputs  
are configured as fully differential, bipolar inputs with a gain of  
1. A quartz crystal provides the master clock source for the part.  
It may be necessary to connect capacitors (C1 and C2 in the  
diagram) on the crystal to ensure that it does not oscillate at over-  
tones of its fundamental operating frequency. The values of ca-  
pacitors will vary depending on the manufacturer’s specifications.  
V
TO ␮P  
AD7741  
COUNTER  
IN  
GATE  
SIGNAL  
CLKIN  
FREQUENCY  
DIVIDER  
CLOCK  
GENERATOR  
Figure 10. A/D Conversion Using the AD7741 VFC  
+5V  
4096x T  
CLOCK  
f
CLKIN  
V
PD  
DD  
V
V
1
2
IN  
DIFF  
REFOUT  
REFIN  
INPUT 1  
IN  
f
OUT  
V
V
3
4
IN  
AD7742  
DIFF  
INPUT 2  
f
OUT  
IN  
GATE  
T
GATE  
GND  
UNI/BIP  
GAIN  
A0  
A1  
CHANNEL  
SELECT  
Figure 11. Waveforms in an A/D Converter Using a VFC  
The clock frequency and the gate time determine the resolution  
of such an ADC. If 12-bit resolution is required and fCLKIN is  
5 MHz (therefore, fOUT max is 2.25 MHz), the minimum gate  
time required is calculated as follows:  
CLKIN  
CLKOUT  
C1  
C2  
N counts at Full Scale (2.25 MHz) will take  
(N/2.25 × 106) seconds = minimum gate time.  
Figure 9. Basic Connection Diagram  
A/D Conversion Techniques Using the AD7741/AD7742  
When used as an ADC, VFCs provide certain advantages in-  
cluding accuracy, linearity and being inherently monotonic. The  
AD7741/AD7742 has a true integrating input which smooths  
out noise peaks.  
N is the total number of codes for a given resolution; 4096 for  
12 bits  
minimum gate time = (4096/2.25 × 106) sec = 1.820 ms.  
Since TGATE × fOUT max = number of counts at full scale, a  
faster conversion with the same resolution can be performed  
with a higher fOUT max. This high fOUT max (3 MHz) is a main  
feature of the AD7741/AD7742.  
The most popular method of using a VFC in an A/D system is  
to count the output pulses of fOUT for a fixed gate interval (see  
Figure 10). This fixed gate interval should be generated by  
dividing down the clock input frequency. This ensures that any  
errors due to clock jitter or clock frequency drift are eliminated.  
The ratio of the fOUT to the clock frequency is what is important  
here, not the absolute value of fOUT. The frequency division can  
be done by a binary counter where fCLKIN is the CLK input.  
If the output frequency is measured by counting pulses gated to  
a signal which is derived from the clock, the clock stability is  
unimportant and the device simply performs as a voltage-  
controlled frequency divider, producing a high resolution ADC.  
The inherent monotonicity of the transfer function and wide  
range of input clock frequencies allows the conversion time and  
resolution to be optimized for specific applications.  
Figure 11 shows the waveforms of fCLKIN, fOUT and the Gate  
signal. A counter counts the rising edges of fOUT while the Gate  
signal is high. Since the gate interval is not synchronized with  
fOUT, there is a possibility of a counting inaccuracy. Depending  
on fOUT, an error of one count may occur.  
There is another parameter is taken into account when choosing  
the length of the gate interval. Because the integration period of  
the system is equal to the gate interval, any interfering signal can  
be rejected by counting for an integer number of periods of the  
interfering signal. For example, a gate interval of 100 ms will  
give normal-mode rejection of 50 Hz and 60 Hz signals.  
–10–  
REV. 0  
1...789101112

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