Datasheet > AD7706BRZ-REEL1

AD7706BRZ-REEL1

更新时间： 2022-04-11 23:23:08

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
44页	401K
描述
3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs

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AD7706BRZ-REEL1 数据手册

AD7705/AD7706

Parameter

B Version¹

Unit

Conditions/Comments

POWER REQUIREMENTS

V_DDVoltage

2.7 to 3.3

V min to V max For specified performance

Power Supply Currents¹⁷

Digital I/Ps = 0 V or V_DD, external MCLK IN and CLKDIS = 1

BUF bit = 0, f_CLKIN= 1 MHz, gains of 1 to 128

BUF bit = 1, f_CLKIN= 1 MHz, gains of 1 to 128

BUF bit = 0, f_CLKIN= 2.4576 MHz, gains of 1 to 4

BUF bit = 0, f_CLKIN= 2.4576 MHz, gains of 8 to 128

BUF bit = 1, f_CLKIN= 2.4576 MHz, gains of 1 to 4

BUF bit = 1, f_CLKIN= 2.4576 MHz, gains of 8 to 128

0.32

0.6

0.4

0.6

0.7

1.1

mA max

V_DDVoltage

Power Supply Currents¹⁷

4.75 to 5.25

V min to V max For specified performance

Digital I/Ps = 0 V or V_DD, external MCLK IN and CLKDIS = 1

0.45

0.7

0.6

0.85

0.9

1.3

mA max

μA max

dB typ

BUF bit = 0, f_CLKIN= 1 MHz, gains of 1 to 128

BUF bit = 1, f_CLKIN= 1 MHz, gains of 1 to 128

BUF bit = 0, f_CLKIN= 2.4576 MHz, gains of 1 to 4

BUF bit = 0, f_CLKIN= 2.4576 MHz, gains of 8 to 128

BUF bit = 1, f_CLKIN= 2.4576 MHz, gains of 1 to 4

BUF bit = 1, f_CLKIN= 2.4576 MHz, gains of 8 to 128

External MCLK IN = 0 V or V_DD, V_DD= 5 V, see Figure 12

External MCLK IN = 0 V or V_DD, V_DD= 3 V

Standby (Power-Down) Current¹⁸

Power Supply Rejection^{19, 20}

¹Temperature range is −40°C to +85°C.

²These numbers are established from characterization or design data at initial product release.

³A calibration is effectively a conversion; therefore, these errors are of the order of the conversion noise shown in Table 5 and Table 7. This applies after calibration at

the temperature of interest.

⁴Recalibration at any temperature removes these drift errors.

⁵Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.

⁶Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.

⁷Gain error does not include zero-scale errors. It is calculated as (full-scale error – unipolar offset error) for unipolar ranges and (full-scale error - bipolar zero error) for

bipolar ranges.

⁸Gain drift does not include unipolar offset drift or bipolar zero drift. It is effectively the drift of the part if only zero-scale calibrations are performed.

⁹This common-mode voltage range is allowed, provided that the input voltage on analog inputs is not more positive than V_DD+ 30 mV or more negative than

GND − 100 mV. Parts are functional with voltages down to GND − 200 mV, but with increased leakage at high temperatures.

¹⁰The AD7705/AD7706 can tolerate absolute analog input voltages down to GND − 200 mV, but the leakage current increases.

¹¹The analog input voltage range on AIN(+) is given with respect to the voltage on AIN(−) on the AD7705, and with respect to the voltage of the COMMON input on the

AD7706. The absolute voltage on the analog inputs should not be more positive than V_DD+ 30 mV, or more negative than GND − 100 mV for specified performance.

Input voltages of GND − 200 mV can be accommodated, but with increased leakage at high temperatures.

= REFIN(+) − REFIN(−).

REF

¹³These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.

¹⁴Sample tested at 25°C to ensure compliance.

¹⁵After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s.

¹⁶These calibration and span limits apply, provided that the absolute voltage on the analog inputs does not exceed V_DD+ 30 mV or go more negative than

GND − 100 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

¹⁷When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the V_DDcurrent and power dissipation varies depending on the

crystal or resonator type (see Clocking and Oscillator Circuit section).

¹⁸If the external master clock continues to run in standby mode, the standby current increases to 150 μA typical at 5 V and 75 μA at 3 V. When using a crystal or ceramic

resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode, and the power dissipation depends on the

crystal or resonator type (see Standby Mode section).

¹⁹Measured at dc and applies in the selected pass band. PSRR at 50 Hz exceeds 120 dB, with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB, with filter

notches of 20 Hz or 60 Hz.

²⁰PSRR depends on both gain and V_DD, as follows:

Gain

V_DD= 3 V

V_DD= 5 V

8 to 128

Rev. C | Page 7 of 44

1...4 5 678 9 10...44

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