5秒后页面跳转
AD7706BRZ-REEL1 PDF预览

AD7706BRZ-REEL1

更新时间: 2022-04-11 23:23:08
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
44页 401K
描述
3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs

AD7706BRZ-REEL1 数据手册

 浏览型号AD7706BRZ-REEL1的Datasheet PDF文件第3页浏览型号AD7706BRZ-REEL1的Datasheet PDF文件第4页浏览型号AD7706BRZ-REEL1的Datasheet PDF文件第5页浏览型号AD7706BRZ-REEL1的Datasheet PDF文件第7页浏览型号AD7706BRZ-REEL1的Datasheet PDF文件第8页浏览型号AD7706BRZ-REEL1的Datasheet PDF文件第9页 
AD7705/AD7706  
Parameter  
B Version1  
Gain ꢀ fCLKIN/64  
fCLKIN/8  
Unit  
Conditions/Comments  
For gains of 1 to 4  
For gains of 8 to 128  
AIN Input Sampling Rate, fS  
Reference Input Range  
REF IN(+) − REF IN(−) Voltage  
1/1.75  
1/3.5  
V min/V max  
V min/V max  
VDD = 2.7 V to 3.3 V  
VREF = 1.225 1% for specified performance  
VDD = 4.75 V to 5.25 V  
REF IN(+) − REF IN(−) Voltage  
V
REF = 2.5 1% for specified performance  
REF IN Input Sampling Rate, fS  
LOGIC INPUTS  
fCLKIN/64  
Input Current  
All Inputs, Except MCLK IN  
MCLK IN  
1
10  
μA max  
μA max  
Typically 20 nA  
Typically 2 μA  
All Inputs, Except SCLK and MCLK IN  
Input Low Voltage, VINL  
0.8  
0.4  
2.0  
V max  
V max  
V min  
VDD = 5 V  
VDD = 3 V  
VDD = 3 V and 5 V  
VDD = 5 V nominal  
Input High Voltage, VINH  
SCLK Only (Schmitt-Triggered Input)  
VT+  
VT−  
VT+ − VT−  
1.4/3  
0.8/1.4  
0.4/0.8  
V min/V max  
V min/V max  
V min/V max  
SCLK Only (Schmitt-Triggered Input)  
VT+  
VT−  
VDD = 3 V nominal  
1/2  
0.4/1.1  
0.375/0.8  
V min/V max  
V min/V max  
V min/V max  
VT+ − VT−  
MCLK IN Only  
VDD = 5 V nominal  
VDD = 3 V nominal  
Input Low Voltage, VINL  
Input High Voltage, VINH  
MCLK IN Only  
0.8  
3.5  
V max  
V min  
Input Low Voltage, VINL  
Input High Voltage, VINH  
LOGIC OUTPUTS (Including MCLK OUT)  
Output Low Voltage, VOL  
Output Low Voltage, VOL  
Output High Voltage, VOH  
Output High Voltage, VOH  
Floating State Leakage Current  
Floating State Output Capacitance14  
Data Output Coding  
0.4  
2.5  
V max  
V min  
0.4  
0.4  
4
VDD − 0.6  
10  
9
V max  
V max  
V min  
V min  
μA max  
pF typ  
ISINK = 800 μA, except for MCLK OUT;13 VDD = 5 V  
ISINK = 100 μA, except for MCLK OUT;13 VDD = 3 V  
ISOURCE = 200 μA, except for MCLK OUT;13 VDD = 5 V  
ISOURCE = 100 μA, except for MCLK OUT;13 VDD = 3 V  
Binary  
Offset binary  
Unipolar mode  
Bipolar mode  
SYSTEM CALIBRATION  
Positive Full-Scale Limit15  
Negative Full-Scale Limit15  
Offset Limit15  
(1.05 ꢀ VREF)/gain  
−(1.05 ꢀ VREF)/gain  
−(1.05 ꢀ VREF)/gain  
(0.8 ꢀ VREF)/gain  
(2.1 ꢀ VREF)/gain  
V max  
V max  
V max  
V min  
V max  
Gain is the selected PGA gain (1 to 128)  
Gain is the selected PGA gain (1 to 128)  
Gain is the selected PGA gain (1 to 128)  
Gain is the selected PGA gain (1 to 128)  
Gain is the selected PGA gain (1 to 128)  
Input Span16  
Rev. C | Page 6 of 44  

与AD7706BRZ-REEL1相关器件

型号 品牌 描述 获取价格 数据表
AD7706BRZ-REEL7 ROCHESTER 3-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16, 0.300 INCH, LEAD FREE, MS-013AA, SOIC-

获取价格

AD7706BRZ-REEL71 ADI 3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs

获取价格

AD7706EB ADI 3 V/5 V 1 mW 2-/3-Channel 16-Bit Sigma-Delta ADCs(264.12 k)

获取价格

AD7707 ADI 3 V/5 V, +-10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC

获取价格

AD7707_17 ADI 3-Channel 16-Bit, Sigma-Delta ADC

获取价格

AD7707BR ADI 3 V/5 V, +-10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC

获取价格